;bdiGDB configuration file for P5040-DS ;-------------------------------------- ; ; [INIT] ; WREG MSR 0x80001002 ;set 64-bit mode ; ; Setup TLB1 for core #0 ; MAS1 MAS2 MAS0/MAS7 MAS3 #0 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #0 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX ; WREG mas2 0x00000064_0x00000000 ;set MAS2 upper word WTLB 0x80000700_0xfe00000a 0x10060000_0xfe00003f ;1/6: 64_ff000000->0_ff000000 16MB -I-G- RWXRWX WREG mas2 0x00000000_0x00000000 ;set MAS2 upper word ; ;========================================================================================= ; Setup TLB0 (for test purpose only) ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000100_0x90000000 0x00000001_0x0000003f ;WAY0: 90000000->1_00000000 4KB ----- RWXRWX WTLB 0x80000100_0x90001000 0x00000001_0x0000103f ;WAY0: 90001000->1_00001000 4KB ----- RWXRWX WTLB 0x80000100_0x90002000 0x00000001_0x0000203f ;WAY0: 90002000->1_00002000 4KB ----- RWXRWX WTLB 0x80000100_0x90003000 0x00000001_0x0000303f ;WAY0: 90003000->1_00003000 4KB ----- RWXRWX ; WTLB 0x80000100_0x91000000 0x00010001_0x0010003f ;WAY1: 91000000->1_00100000 4KB ----- RWXRWX WTLB 0x80000100_0x92001000 0x00020001_0x0020103f ;WAY2: 92001000->1_00201000 4KB ----- RWXRWX WTLB 0x80000100_0x93002000 0x00030001_0x0030203f ;WAY3: 93002000->1_00302000 4KB ----- RWXRWX WTLB 0x80000100_0x94003000 0x00020001_0x0040303f ;WAY2: 94003000->1_00403000 4KB ----- RWXRWX ; WTLB 0x80000100_0x9107f000 0x00000001_0x0010003f ;WAY0: 9107f000->1_00100000 4KB ----- RWXRWX WTLB 0x80000100_0x920ff000 0x00010001_0x0020103f ;WAY1: 920ff000->1_00201000 4KB ----- RWXRWX WTLB 0x80000100_0x931ff000 0x00020001_0x0030203f ;WAY2: 931ff000->1_00302000 4KB ----- RWXRWX WTLB 0x80000100_0x942ff000 0x00030001_0x0040303f ;WAY3: 942ff000->1_00403000 4KB ----- RWXRWX ; ;========================================================================================= ; ; Initialize LAWBAR's WREG lawbarh0 0x00000000 ;LAWBAR0 : Flash @0_e0000000 WREG lawbarl0 0xe0000000 WREG lawar0 0x81f0001b ;LAWAR0 : eLBC 256MB ; WREG lawbarh1 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 WREG lawbarl1 0x80000000 WREG lawar1 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB ; WREG lawbarh31 0x00000000 ;LAWBAR31: SDRAM @0_00000000 WREG lawbarl31 0x00000000 WREG lawar31 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WREG cpc1_srcr1 0x00000000 ;CPC1_SRCR1 : high address WREG cpc1_srcr0 0x8000000b ;CPC1_SRCR0 : all 32 ways as SRAM WREG cpc1_csr0 0x80000000 ;CPC1_CSR0 : CPC enable WREG cpc1_hdbcr0 0x08000000 ;CPC1_HDBCR0: Speculation disable ; ; Release cores for booting WREG brr 0x0000000f ;BRR: release cores ; ; Setup TLB1 for core #0,#1,#2,#3 ; MAS1 MAS2 MAS0/MAS7 MAS3 #1 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #1 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX #2 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #2 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX #3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #3 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX ; ; write DNH instruction to default vector WM32 0x80000000 0x4c00018c ;catch default vector ; ; write a loop to CPC1/SRAM WM32 0x80000100 0x386003e8 ;li r3,1000 WM32 0x80000104 0x38800000 ;li r4,0 WM32 0x80000108 0x38a00000 ;li r5,0 WM32 0x8000010c 0x38a50008 ;addi r5,r5,8 WM32 0x80000110 0x38840008 ;addi r4,r4,8 WM32 0x80000114 0x3463ffff ;addic. r3,r3,-1 WM32 0x80000118 0x4082fff4 ;bne bc WM32 0x8000011c 0x4bffffe4 ;b b0 WM32 0x80000120 0x60000000 ;nop WM32 0x80000124 0x60000000 ;nop ; ; set PC to start of loop #0 WREG pc 0x80000100 #1 WREG pc 0x80000100 #2 WREG pc 0x80000100 #3 WREG pc 0x80000100 ; ; set default vector #0 WREG ivpr 0x80000000 #1 WREG ivpr 0x80000000 #2 WREG ivpr 0x80000000 #3 WREG ivpr 0x80000000 ; ; limit access to valid memory space #0 MMAP 0x80000000 0x800fffff #0 MMAP 0xfe000000 0xfeffffff #0 MMAP 0x00020000_0x00000000 0x00020000_0xffffffff ;DCSR space ; #1 MMAP 0x80000000 0x800fffff #1 MMAP 0xfe000000 0xfeffffff ; #2 MMAP 0x80000000 0x800fffff #2 MMAP 0xfe000000 0xfeffffff ; #3 MMAP 0x80000000 0x800fffff #3 MMAP 0xfe000000 0xfeffffff ; [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 2 ;use 4 MHz JTAG clock RESET HARD 1000 ;assert reset for 1 seconds WAKEUP 200 ;give reset time to complete ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE P4080 5 0 !!!! ;======================================================== ; ; CoreID#0 parameters (active vCPU after reset) #0 CPUTYPE P5040 0 0 ;Core#0 / SOC#0 #0 EDBCR0 EDM DNH EFT ;set run parameters #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint ; ; CoreID#1 parameters #1 CPUTYPE P5040 1 0 ;Core#1 / SOC#0 #1 EDBCR0 EDM DNH EFT ;set run parameters #1 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #2 CPUTYPE P5040 2 0 ;Core#2 / SOC#0 #2 EDBCR0 EDM DNH EFT ;set run parameters #2 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #3 CPUTYPE P5040 3 0 ;Core#3 / SOC#0 #3 EDBCR0 EDM DNH EFT ;set run parameters #3 STARTUP HALT ;halt at the reset vector ; [HOST] ;DEBUGPORT 2001 NS-MT ;Non-stop Multi-Threaded Mode ; FILE E:\temp\dump256k.bin FORMAT BIN 0x80000000 ; #0 PROMPT P5040#0> #1 PROMPT P5040#1> #2 PROMPT P5040#2> #3 PROMPT P5040#3> ; [FLASH] [REGS] FILE $regP5040.def ;