;Register definition for MGT5100 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IMMx indirect memory mapped register ; x = 1..4 ; the addr and data address is defined in the configuration file ; e.g. IMM1 0xFEC00000 0xFEE00000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; xer SPR 1 lr SPR 8 ctr SPR 9 dsisr SPR 18 dar SPR 19 dec SPR 22 sdr1 SPR 25 srr0 SPR 26 srr1 SPR 27 csrr0 SPR 58 csrr1 SPR 59 ; tbl SPR 268 tbu SPR 269 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 sprg4 SPR 276 sprg5 SPR 277 sprg6 SPR 278 sprg7 SPR 279 ear SPR 282 pvr SPR 287 ; ibat0u SPR 528 ibat0l SPR 529 ibat1u SPR 530 ibat1l SPR 531 ibat2u SPR 532 ibat2l SPR 533 ibat3u SPR 534 ibat3l SPR 535 ; dbat0u SPR 536 dbat0l SPR 537 dbat1u SPR 538 dbat1l SPR 539 dbat2u SPR 540 dbat2l SPR 541 dbat3u SPR 542 dbat3l SPR 543 ; ibat4u SPR 560 ibat4l SPR 561 ibat5u SPR 562 ibat5l SPR 563 ibat6u SPR 564 ibat6l SPR 565 ibat7u SPR 566 ibat7l SPR 567 ; dbat4u SPR 568 dbat4l SPR 569 dbat5u SPR 570 dbat5l SPR 571 dbat6u SPR 572 dbat6l SPR 573 dbat7u SPR 574 dbat7l SPR 575 ; dmiss SPR 976 dcmp SPR 977 imiss SPR 980 icmp SPR 981 rpa SPR 982 ; dabr2 SPR 1000 dbcr SPR 1001 ibcr SPR 1002 ; hid0 SPR 1008 hid1 SPR 1009 iabr SPR 1010 hid2 SPR 1011 ; dabr SPR 1013 iabr2 SPR 1018 ; ; ; DMM1 must be set to the internal memory base address ; ; IPIB base address registers ; mbar DMM1 0x000 32 cs0str DMM1 0x004 32 cs0spr DMM1 0x008 32 cs1str DMM1 0x00c 32 cs1spr DMM1 0x010 32 cs2str DMM1 0x014 32 cs2spr DMM1 0x018 32 cs3str DMM1 0x01c 32 cs3spr DMM1 0x020 32 cs4str DMM1 0x024 32 cs4spr DMM1 0x028 32 cs5str DMM1 0x02c 32 cs5spr DMM1 0x030 32 sdramstr DMM1 0x034 32 sdramspr DMM1 0x038 32 pci1str DMM1 0x03c 32 pci1spr DMM1 0x040 32 pci2str DMM1 0x044 32 pci2spr DMM1 0x048 32 bootstr DMM1 0x04c 32 bootspr DMM1 0x050 32 adren DMM1 0x054 32 ; ; SDRAM Controller ; sdrmode DMM1 0x100 32 sdrctrl DMM1 0x104 32 sdrcnf1 DMM1 0x108 32 sdrcnf2 DMM1 0x10c 32 sdrcnf3 DMM1 0x110 32 ; ; Clock Distribution Module ; cidr DMM1 0x200 32 crcr DMM1 0x204 32 cbr DMM1 0x208 32 cmcsr DMM1 0x20c 8 cxcsr DMM1 0x20d 8 cicsr DMM1 0x20e 8 clcsr DMM1 0x20f 8 ce48er DMM1 0x210 8 cfder DMM1 0x211 8 cfdcr DMM1 0x212 16 ccer DMM1 0x214 32 codr DMM1 0x218 32 ccscr DMM1 0x21c 32 csrr DMM1 0x220 32 cpllsr DMM1 0x224 32 ; ; Local Plus Bus Controller ; cs0cr DMM1 0x300 32 cs1cr DMM1 0x304 32 cs2cr DMM1 0x308 32 cs3cr DMM1 0x30c 32 cs4cr DMM1 0x310 32 cs5cr DMM1 0x314 32 csctrlr DMM1 0x318 32 cssr DMM1 0x31c 32 ;