;Register definition for MPC565 ;============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 pc SPR 26 ; is SRR0 ; xer SPR 1 lr SPR 8 ctr SPR 9 dsisr SPR 18 dar SPR 19 dec SPR 22 srr0 SPR 26 srr1 SPR 27 ; cmpa SPR 144 cmpb SPR 145 cmpc SPR 146 cmpd SPR 147 icr SPR 148 der SPR 149 counta SPR 150 countb SPR 151 cmpe SPR 152 cmpf SPR 153 cmpg SPR 154 cmph SPR 155 lctrl1 SPR 156 lctrl2 SPR 157 ictrl SPR 158 bar SPR 159 ; tbl SPR 268 tbu SPR 269 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 pvr SPR 287 ; mi_gra SPR 528 eibadr SPR 529 l2u_gra SPR 536 bbcmcr SPR 560 l2u_mcr SPR 568 ; immr SPR 638 ; mi_rba0 SPR 784 mi_rba1 SPR 785 mi_rba2 SPR 786 mi_rba3 SPR 787 l2u_rb0 SPR 792 l2u_rb1 SPR 793 l2u_rb2 SPR 794 l2u_rb3 SPR 795 mi_ra0 SPR 816 mi_ra1 SPR 817 mi_ra2 SPR 818 mi_ra3 SPR 819 l2u_ra0 SPR 824 l2u_ra1 SPR 825 l2u_ra2 SPR 826 l2u_ra3 SPR 827 ; fpecr SPR 1022 ; ; ; DMM1 must be set to the internal memory base address ; ; USIU siumcr DMM1 0x2fc000 32 sypcr DMM1 0x2fc004 32 swsr DMM1 0x2fc00e 16 sipend DMM1 0x2fc010 32 simask DMM1 0x2fc014 32 siel DMM1 0x2fc018 32 sivec DMM1 0x2fc01c 32 tesr DMM1 0x2fc020 32 sgpiodt1 DMM1 0x2fc024 32 sgpiodt2 DMM1 0x2fc028 32 sgpiocr DMM1 0x2fc02c 32 emcr DMM1 0x2fc030 32 pdmcr DMM1 0x2fc03c 16 sipend2 DMM1 0x2fc040 16 sipend3 DMM1 0x2fc044 16 simask2 DMM1 0x2fc048 32 simask3 DMM1 0x2fc04c 32 sisr2 DMM1 0x2fc050 32 sisr3 DMM1 0x2fc054 32 ; ; Memory Controller br0 DMM1 0x2fc100 32 or0 DMM1 0x2fc104 32 br1 DMM1 0x2fc108 32 or1 DMM1 0x2fc10c 32 br2 DMM1 0x2fc110 32 or2 DMM1 0x2fc114 32 br3 DMM1 0x2fc118 32 or3 DMM1 0x2fc11c 32 dmbr DMM1 0x2fc140 32 dmor DMM1 0x2fc144 32 mstat DMM1 0x2fc178 16 ; ; System Integration Timer tbscr DMM1 0x2fc200 16 tbref0 DMM1 0x2fc204 32 tbref1 DMM1 0x2fc208 32 rtcsc DMM1 0x2fc220 16 rtc DMM1 0x2fc224 32 rtsec DMM1 0x2fc228 32 rtcal DMM1 0x2fc22c 32 piscr DMM1 0x2fc240 16 pitc DMM1 0x2fc244 32 pitr DMM1 0x2fc248 32 ; ; Clocks and Reset sccr DMM1 0x2fc280 32 plprcr DMM1 0x2fc284 32 rsr DMM1 0x2fc288 16 colir DMM1 0x2fc28c 16 vsrcr DMM1 0x2fc290 16 ; ; System Integration Timer Keys tbscrk DMM1 0x2fc300 32 tbref0k DMM1 0x2fc304 32 tbref1k DMM1 0x2fc308 32 tbk DMM1 0x2fc30c 32 rtcsck DMM1 0x2fc320 32 rtck DMM1 0x2fc324 32 rtseck DMM1 0x2fc328 32 rtcalk DMM1 0x2fc32c 32 piscrk DMM1 0x2fc340 32 pitck DMM1 0x2fc344 32 ; ; Clocks and Reset Keys sccrk DMM1 0x2fc380 32 plprcrk DMM1 0x2fc384 32 rsrk DMM1 0x2fc388 32 ;