; bdiGDB configuration for Samsung SMDK2400 evaluation board ; ---------------------------------------------------------- ; [INIT] ; WM32 0x15300000 0x00008000 ;WTCON: disable watch dog ; ; Setup memory controller based on 24XMON WM32 0x14000000 0x22111122 ;BWSCON WM32 0x14000004 0x00000700 ;BANKCON0 WM32 0x14000008 0x00000700 ;BANKCON1 WM32 0x1400000C 0x00000700 ;BANKCON2 WM32 0x14000010 0x00000700 ;BANKCON3 WM32 0x14000014 0x00000700 ;BANKCON4 WM32 0x14000018 0x00000700 ;BANKCON5 WM32 0x1400001C 0x00018005 ;BANKCON6 WM32 0x14000020 0x00018005 ;BANKCON7 WM32 0x14000024 0x008e0459 ;REFRESH WM32 0x14000028 0x00000010 ;BANKSIZE WM32 0x1400002C 0x00000030 ;MRSRB6 WM32 0x14000030 0x00000030 ;MRSRB7 ; ;Setup MMU and enable cache, Translation table at 0x0C004000 ;Map SDRAM to 0x00000000 ; WCP15 0x51af 0x0C004000 ;set Inst Translation Base Address WCP15 0x52af 0x0C004000 ;set Data Translation Base Address WCP15 0x71af 0xFFFFFFFF ;set Inst Domain Access Control WCP15 0x72af 0xFFFFFFFF ;set Data Domain Access Control WM32 0x0C004000 0x0C000C1E ;MMU: 0x00000000, cacheable, bufferable WM32 0x0C004004 0x0C100C1E ;MMU: 0x00100000, cacheable, bufferable WM32 0x0C004008 0x0C200C1E ;MMU: 0x00200000, cacheable, bufferable WM32 0x0C00400C 0x0C300C1E ;MMU: 0x00300000, cacheable, bufferable WM32 0x0C004010 0x0C400C1E ;MMU: 0x00400000, cacheable, bufferable WM32 0x0C004014 0x0C500C1E ;MMU: 0x00500000, cacheable, bufferable WM32 0x0C004018 0x0C600C1E ;MMU: 0x00600000, cacheable, bufferable WM32 0x0C00401C 0x0C700C1E ;MMU: 0x00700000, cacheable, bufferable WM32 0x0C004020 0x0C800C1E ;MMU: 0x00800000, cacheable, bufferable WM32 0x0C004024 0x0C900C1E ;MMU: 0x00900000, cacheable, bufferable WM32 0x0C004028 0x0CA00C1E ;MMU: 0x00A00000, cacheable, bufferable WM32 0x0C00402C 0x0CB00C1E ;MMU: 0x00B00000, cacheable, bufferable WM32 0x0C004030 0x0CC00C1E ;MMU: 0x00C00000, cacheable, bufferable WM32 0x0C004034 0x0CD00C1E ;MMU: 0x00D00000, cacheable, bufferable WM32 0x0C004038 0x0CE00C1E ;MMU: 0x00E00000, cacheable, bufferable WM32 0x0C00403C 0x0CF00C1E ;MMU: 0x00F00000, cacheable, bufferable ; WM32 0x0C004500 0x14000C12 ;MMU: 0x14000000, non cacheable, non bufferable WM32 0x0C004504 0x14100C12 ;MMU: 0x14100000, non cacheable, non bufferable WM32 0x0C004508 0x14200C12 ;MMU: 0x14200000, non cacheable, non bufferable WM32 0x0C00450C 0x14300C12 ;MMU: 0x14300000, non cacheable, non bufferable WM32 0x0C004510 0x14400C12 ;MMU: 0x14400000, non cacheable, non bufferable WM32 0x0C004514 0x14500C12 ;MMU: 0x14500000, non cacheable, non bufferable WM32 0x0C004518 0x14600C12 ;MMU: 0x14600000, non cacheable, non bufferable WM32 0x0C00451C 0x14700C12 ;MMU: 0x14700000, non cacheable, non bufferable WM32 0x0C004520 0x14800C12 ;MMU: 0x14800000, non cacheable, non bufferable WM32 0x0C004524 0x14900C12 ;MMU: 0x14900000, non cacheable, non bufferable WM32 0x0C004528 0x14A00C12 ;MMU: 0x14A00000, non cacheable, non bufferable WM32 0x0C00452C 0x14B00C12 ;MMU: 0x14B00000, non cacheable, non bufferable WM32 0x0C004530 0x14C00C12 ;MMU: 0x14C00000, non cacheable, non bufferable WM32 0x0C004534 0x14D00C12 ;MMU: 0x14D00000, non cacheable, non bufferable WM32 0x0C004538 0x14E00C12 ;MMU: 0x14E00000, non cacheable, non bufferable WM32 0x0C00453C 0x14F00C12 ;MMU: 0x14F00000, non cacheable, non bufferable ; WM32 0x0C004540 0x15000C12 ;MMU: 0x15000000, non cacheable, non bufferable WM32 0x0C004544 0x15100C12 ;MMU: 0x15100000, non cacheable, non bufferable WM32 0x0C004548 0x15200C12 ;MMU: 0x15200000, non cacheable, non bufferable WM32 0x0C00454C 0x15300C12 ;MMU: 0x15300000, non cacheable, non bufferable WM32 0x0C004550 0x15400C12 ;MMU: 0x15400000, non cacheable, non bufferable WM32 0x0C004554 0x15500C12 ;MMU: 0x15500000, non cacheable, non bufferable WM32 0x0C004558 0x15600C12 ;MMU: 0x15600000, non cacheable, non bufferable WM32 0x0C00455C 0x15700C12 ;MMU: 0x15700000, non cacheable, non bufferable WM32 0x0C004560 0x15800C12 ;MMU: 0x15800000, non cacheable, non bufferable WM32 0x0C004564 0x15900C12 ;MMU: 0x15900000, non cacheable, non bufferable WM32 0x0C004568 0x15A00C12 ;MMU: 0x15A00000, non cacheable, non bufferable WM32 0x0C00456C 0x15B00C12 ;MMU: 0x15B00000, non cacheable, non bufferable WM32 0x0C004570 0x15C00C12 ;MMU: 0x15C00000, non cacheable, non bufferable WM32 0x0C004574 0x15D00C12 ;MMU: 0x15D00000, non cacheable, non bufferable WM32 0x0C004578 0x15E00C12 ;MMU: 0x15E00000, non cacheable, non bufferable WM32 0x0C00457C 0x15F00C12 ;MMU: 0x15F00000, non cacheable, non bufferable ; WCP15 1 0x0000107D ;enable MMU, Caches and Write Buffer ; WGPR 11 0x00000020 ;set frame pointer to free RAM WM32 0x00000020 0x00000028 ;dummy stack frame ; [TARGET] CPUTYPE ARM920T CLOCK 1 ;JTAG clock (0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz) ;STARTUP STOP 6000 ;let the monitor setup the memory controller. ENDIAN LITTLE ;memory model (LITTLE | BIG) WORKSPACE 0x00000020 ;workspace in target RAM for fast download VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset BREAKMODE SOFT 0xDFFFDFFF ;SOFT or HARD, ARM / Thumb break code ;BREAKMODE SOFT 0xef180000 ;SOFT or HARD (X-Tools V1.0 break code) ;SIO 7 9600 ;TCP port for serial IO ;DCC 7 ;TCP port for DCC I/O [HOST] IP 151.120.25.119 FILE E:\cygwin\home\bdidemo\arm\vxworks FORMAT COFF ;FILE E:\cygwin\home\bdidemo\arm\bin_sem0.exe ;FILE E:\cygwin\home\bdidemo\arm\test0.elf ;FORMAT ELF LOAD MANUAL ;load VxWorks code MANUAL or AUTO after reset [FLASH] [REGS] FILE E:\cygwin\home\bdidemo\arm\regS2400.def