;Register definition for STR912F
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
;  Numbers for 966E:
;  +-------+-------+-------+-------+
;  | | | | | | | | | | | | | | | | |
;  +-------+-----+-+-----+-+-------+ i = instruction (bit 32)
;  |0 0 0 0|0 0 0|i|0 0 0|x|  nbr  | x = reg 6 extension (bit 37)
;  +-------+-----+-+-----+-+-------+
;
;
id		CP15    0x0000          32      ;ID code
control 	CP15    0x0001          32      ;Control
;
;
; FMI registers
;
fmi_bbsr        MM      0x54000000      32
fmi_nbbsr       MM      0x54000004      32
fmi_bbadr       MM      0x5400000C      32
fmi_nbbadr      MM      0x54000010      32
fmi_cr	        MM      0x54000018      32
fmi_sr	        MM      0x5400001C	32
fmi_bce5addr    MM      0x54000020      32
;
; EMI registers
;
emi_icr1        MM      0x74000000      32
emi_rcr1        MM      0x74000004      32
emi_wcr1        MM      0x74000008      32
emi_oecr1       MM      0x7400000C      32
emi_wecr1       MM      0x74000010      32
emi_bcr1        MM      0x74000014      32
emi_icr2        MM      0x74000020      32
emi_rcr2        MM      0x74000024      32
emi_wcr2        MM      0x74000028      32
emi_oecr2       MM      0x7400002C      32
emi_wecr2       MM      0x74000030      32
emi_bcr2        MM      0x74000034      32
emi_icr3        MM      0x74000040      32
emi_rcr3        MM      0x74000044      32
emi_wcr3        MM      0x74000048      32
emi_oecr3       MM      0x7400004C      32
emi_wecr3       MM      0x74000050      32
emi_bcr3        MM      0x74000054      32
emi_icr0        MM      0x740000E0      32
emi_rcr0        MM      0x740000E4      32
emi_wcr0        MM      0x740000E8      32
emi_oecr0       MM      0x740000EC      32
emi_wecr0       MM      0x740000F0      32
emi_bcr0        MM      0x740000F4      32
;
; SCU registers
;
scu_clkcntr     MM      0x5C002000      32
scu_pllconf     MM      0x5C002004      32
scu_sysstatus   MM      0x5C002008      32
scu_pwrmng      MM      0x5C00200C      32
scu_itcmsk      MM      0x5C002010      32
scu_pcgr0       MM      0x5C002014      32
scu_pcgr1       MM      0x5C002048      32
scu_prr0        MM      0x5C00201C      32
scu_prr1        MM      0x5C002020      32
scu_mgr0        MM      0x5C002024      32
scu_mgr1        MM      0x5C002028      32
scu_pecgr0      MM      0x5C00202C      32
scu_pecgr1      MM      0x5C002030      32
scu_scr0        MM      0x5C002034      32
scu_scr1        MM      0x5C002038      32
scu_scr2        MM      0x5C00203C      32
scu_gpioout0    MM      0x5C002044      32
scu_gpioout1    MM      0x5C002048      32
scu_gpioout2    MM      0x5C00204C      32
scu_gpioout3    MM      0x5C002050      32
scu_gpioout4    MM      0x5C002054      32
scu_gpioout5    MM      0x5C002058      32
scu_gpioout6    MM      0x5C00205C      32
scu_gpioout7    MM      0x5C002060      32
scu_gpioin0     MM      0x5C002064      32
scu_gpioin1     MM      0x5C002068      32
scu_gpioin2     MM      0x5C00206C      32
scu_gpioin3     MM      0x5C002070      32
scu_gpioin4     MM      0x5C002074      32
scu_gpioin5     MM      0x5C002078      32
scu_gpioin6     MM      0x5C00207C      32
scu_gpioin7     MM      0x5C002080      32
scu_gpiotype0   MM      0x5C002084      32
scu_gpiotype1   MM      0x5C002088      32
scu_gpiotype2   MM      0x5C00208C      32
scu_gpiotype3   MM      0x5C002090      32
scu_gpiotype4   MM      0x5C002094      32
scu_gpiotype5   MM      0x5C002098      32
scu_gpiotype6   MM      0x5C00209C      32
scu_gpiotype7   MM      0x5C0020A0      32
scu_gpiotype8   MM      0x5C0020A4      32
scu_gpiotype9   MM      0x5C0020A8      32
scu_gpioemi     MM      0x5C0020AC      32
scu_wkupsel     MM      0x5C0020B0      32
scu_gpioana     MM      0x5C0020BC      32
;
; GPIO registers
;
gpio0_data      MM      0x580063FC      32
gpio0_dir       MM      0x58006400      32
gpio0_sel       MM      0x58006420      32
;
gpio1_data      MM      0x580073FC      32
gpio1_dir       MM      0x58007400      32
gpio1_sel       MM      0x58007420      32
;
gpio2_data      MM      0x580083FC      32
gpio2_dir       MM      0x58008400      32
gpio2_sel       MM      0x58008420      32
;
gpio3_data      MM      0x580093FC      32
gpio3_dir       MM      0x58009400      32
gpio3_sel       MM      0x58009420      32
;
gpio4_data      MM      0x5800A3FC      32
gpio4_dir       MM      0x5800A400      32
gpio4_sel       MM      0x5800A420      32
;
gpio5_data      MM      0x5800B3FC      32
gpio5_dir       MM      0x5800B400      32
gpio5_sel       MM      0x5800B420      32
;
gpio6_data      MM      0x5800C3FC      32
gpio6_dir       MM      0x5800C400      32
gpio6_sel       MM      0x5800C420      32
;
gpio7_data      MM      0x5800D3FC      32
gpio7_dir       MM      0x5800D400      32
gpio7_sel       MM      0x5800D420      32
;
gpio8_data      MM      0x5800E3FC      32
gpio8_dir       MM      0x5800E400      32
gpio8_sel       MM      0x5800E420      32
;
gpio9_data      MM      0x5800F3FC      32
gpio9_dir       MM      0x5800F400      32
gpio9_sel       MM      0x5800F420      32
;