;Register definition for ARM926E
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
;  Register Numbers for 926E:
;  +-------+-------+-------+-------+
;  | | | | | | | | | | | | | | | | |
;  +-+-----+-+-----+-------+-------+
;  |-|opc_1|-|opc_2|  CRm  |  nbr  |
;  +-+-----+-+-----+-------+-------+
;
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x0100          32      ;Cache type
tcm             CP15    0x0200          32      ;TCM status
control 	CP15    0x0001          32      ;Control
ttb     	CP15    0x0002          32      ;Translation table base
dac     	CP15    0x0003          32      ;Domain access control
dfsr      	CP15    0x0005          32      ;Data fault status
ifsr    	CP15    0x0105          32      ;Inst fault status
far       	CP15    0x0006          32      ;Fault address
;
fcsr      	CP15    0x000d          32      ;Fast context switch PID
context 	CP15    0x010d          32      ;Context ID
;
; Embedded Flash Controller
;
eefc_fmr  	MM	0xFFFFFA00	32
eefc_fcr  	MM	0xFFFFFA04	32
eefc_fsr  	MM	0xFFFFFA08	32
eefc_frr  	MM	0xFFFFFA0C	32
;
; Watchdog Timer
;
wdt_cr  	MM	0xFFFFFD40	32
wdt_mr  	MM	0xFFFFFD44	32
wdt_sr  	MM	0xFFFFFD48	32
;
; Reset Controller
;
rstc_cr 	MM	0xFFFFFD00	32
rstc_sr 	MM	0xFFFFFD04	32
rstc_mr 	MM	0xFFFFFD08	32
;
; Power Management Controller
;
pmc_scer	MM	0xFFFFFC00	32
pmc_scdr	MM	0xFFFFFC04	32
pmc_scsr	MM	0xFFFFFC08	32
pmc_pcer	MM	0xFFFFFC10	32
pmc_pcdr	MM	0xFFFFFC14	32
pmc_pcsr	MM	0xFFFFFC18      32
ckgr_mor	MM	0xFFFFFC20	32
ckgr_mcfr       MM	0xFFFFFC24	32
ckgr_pllar      MM	0xFFFFFC28	32
ckgr_pllbr      MM	0xFFFFFC2C	32
pmc_mckr	MM	0xFFFFFC30	32
pmc_pck0	MM	0xFFFFFC40	32
pmc_pck1	MM	0xFFFFFC44	32
pmc_ier 	MM	0xFFFFFC60	32
pmc_idr 	MM	0xFFFFFC64	32
pmc_sr          MM	0xFFFFFC68	32
pmc_imr 	MM	0xFFFFFC6C	32
pmc_pllicpr 	MM	0xFFFFFC80	32
;
; SDRAM Controller
;
sdramc_mr 	MM	0xFFFFEA00	32
sdramc_tr 	MM	0xFFFFEA04	32
sdramc_cr 	MM	0xFFFFEA08	32
sdramc_lpr	MM	0xFFFFEA10	32
sdramc_ier	MM	0xFFFFEA14	32
sdramc_idr	MM	0xFFFFEA18	32
sdramc_imr	MM	0xFFFFEA1C	32
sdramc_isr	MM	0xFFFFEA20	32
sdramc_mdr	MM	0xFFFFEA24	32
;
; Bus Matrix
;
matrix_mcfg0 	MM	0xFFFFEE00	32
matrix_mcfg1 	MM	0xFFFFEE04	32
matrix_mcfg2 	MM	0xFFFFEE08	32
matrix_mcfg3 	MM	0xFFFFEE0C	32
matrix_mcfg4 	MM	0xFFFFEE10	32
matrix_mcfg5 	MM	0xFFFFEE14	32
matrix_scfg0 	MM	0xFFFFEE40	32
matrix_scfg1 	MM	0xFFFFEE44	32
matrix_scfg2 	MM	0xFFFFEE48	32
matrix_scfg3 	MM	0xFFFFEE4C	32
matrix_scfg4 	MM	0xFFFFEE50	32
matrix_pras0 	MM	0xFFFFEE80	32
matrix_pras1 	MM	0xFFFFEE88	32
matrix_pras2 	MM	0xFFFFEE90	32
matrix_pras3 	MM	0xFFFFEE98	32
matrix_pras4 	MM	0xFFFFEEA0	32
matrix_mrcr  	MM	0xFFFFEF00	32
;
ebi_csa  	MM	0xFFFFEF1C	32
;