;Register definition for Feroceon 946 (Osprey) ;============================================= ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; CP15 CP15 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; ; CP15 Registers ; ; Register Numbers for Fero946: ; +-------+-------+-------+-------+ ; | | | | | | | | | | | | | | | | | ; +-+-----+-+-----+-------+-------+ ; |-|opc_1|-|opc_2| CRm | nbr | ; +-+-----+-+-----+-------+-------+ ; ; id CP15 0x0000 32 ;ID code cache CP15 0x0100 32 ;Cache type tcmsize CP15 0x0200 32 ;Tightly-coupled memor size control CP15 0x0001 32 ;Control dcen CP15 0x0002 32 ;data cacheable bits icen CP15 0x0102 32 ;inst cacheable bits wben CP15 0x0003 32 ;write buffer control dacc CP15 0x0005 32 ;standard data access permission iacc CP15 0x0105 32 ;standard inst access permission xdacc CP15 0x0205 32 ;extended data access permission xiacc CP15 0x0305 32 ;extended inst access permission ; region0 CP15 0x0006 32 ;protection region base/size 0 region1 CP15 0x0016 32 ;protection region base/size 1 region2 CP15 0x0026 32 ;protection region base/size 2 region3 CP15 0x0036 32 ;protection region base/size 3 region4 CP15 0x0046 32 ;protection region base/size 4 region5 CP15 0x0056 32 ;protection region base/size 5 region6 CP15 0x0066 32 ;protection region base/size 6 region7 CP15 0x0076 32 ;protection region base/size 7 ; dlock CP15 0x0009 32 ;data cache lock-down ilock CP15 0x0109 32 ;inst cache lock-down dtcm CP15 0x0019 32 ;data TCM size/location itcm CP15 0x0119 32 ;inst TCM size/location pid CP15 0x010d 32 ;process identifier ;