;Register definition for AT91SAM9261
;===================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
;  Register Numbers for 926E:
;  +-------+-------+-------+-------+
;  | | | | | | | | | | | | | | | | |
;  +-+-----+-+-----+-------+-------+
;  |-|opc_1|-|opc_2|  CRm  |  nbr  |
;  +-+-----+-+-----+-------+-------+
;
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x0100          32      ;Cache type
tcm             CP15    0x0200          32      ;TCM status
control 	CP15    0x0001          32      ;Control
ttb     	CP15    0x0002          32      ;Translation table base
dac     	CP15    0x0003          32      ;Domain access control
dfsr      	CP15    0x0005          32      ;Data fault status
ifsr    	CP15    0x0105          32      ;Inst fault status
far       	CP15    0x0006          32      ;Fault address
;
fcsr      	CP15    0x000d          32      ;Fast context switch PID
context 	CP15    0x010d          32      ;Context ID
;
;
; Reset Controller (RSTC)
;
rstc_cr	        MM	0xFFFFFD00
rstc_sr	        MM	0xFFFFFD04
rstc_mr	        MM	0xFFFFFD08
;
; Real-time Timer (RTT)
;
rtt_mr 	        MM	0xFFFFFD20
rtt_ar 	        MM	0xFFFFFD24
rtt_vr 	        MM	0xFFFFFD28
rtt_sr 	        MM	0xFFFFFD2C
;
; Periodic Interval Timer (PIT)
;
pit_mr          MM	0xFFFFFD30
pit_sr          MM	0xFFFFFD34
pit_pivr        MM	0xFFFFFD38
pit_piir        MM	0xFFFFFD3C
;
; Watchdog Timer (WDT)
;
wdt_cr          MM	0xFFFFFD40
wdt_mr          MM	0xFFFFFD44
wdt_sr          MM	0xFFFFFD48
;
; Shutdown Controller (SHDWC)
;
shdw_cr         MM	0xFFFFFD10
shdw_mr         MM	0xFFFFFD14
shdw_sr         MM	0xFFFFFD18
;
; Bus Matrix
;
matrix_mcfg     MM	0xFFFFEE00
matrix_scfg0    MM	0xFFFFEE04
matrix_scfg1    MM	0xFFFFEE08
matrix_scfg2    MM	0xFFFFEE0C
matrix_scfg3    MM	0xFFFFEE10
matrix_scfg4    MM	0xFFFFEE14
matrix_tcr      MM	0xFFFFEE24
ebi_csa         MM	0xFFFFEE30
usb_pucr        MM	0xFFFFEE34
;
; Static Memory Controller (SMC)
;
smc_setup0      MM	0xFFFFEC00
smc_pulse0      MM	0xFFFFEC04
smc_cycle0      MM	0xFFFFEC08
smc_mode0       MM	0xFFFFEC0C
smc_setup1      MM	0xFFFFEC10
smc_pulse1      MM	0xFFFFEC14
smc_cycle1      MM	0xFFFFEC18
smc_mode1       MM	0xFFFFEC1C
smc_setup2      MM	0xFFFFEC20
smc_pulse2      MM	0xFFFFEC24
smc_cycle2      MM	0xFFFFEC28
smc_mode2       MM	0xFFFFEC2C
smc_setup3      MM	0xFFFFEC30
smc_pulse3      MM	0xFFFFEC34
smc_cycle3      MM	0xFFFFEC38
smc_mode4       MM	0xFFFFEC3C
smc_setup4      MM	0xFFFFEC40
smc_pulse4      MM	0xFFFFEC44
smc_cycle4      MM	0xFFFFEC48
smc_mode4       MM	0xFFFFEC4C
smc_setup5      MM	0xFFFFEC50
smc_pulse5      MM	0xFFFFEC54
smc_cycle5      MM	0xFFFFEC58
smc_mode5       MM	0xFFFFEC5C
smc_setup6      MM	0xFFFFEC60
smc_pulse6      MM	0xFFFFEC64
smc_cycle6      MM	0xFFFFEC68
smc_mode6       MM	0xFFFFEC6C
smc_setup7      MM	0xFFFFEC70
smc_pulse7      MM	0xFFFFEC74
smc_cycle7      MM	0xFFFFEC78
smc_mode7       MM	0xFFFFEC7C
;
; SDRAM Controller
;
sdramc_mr       MM	0xFFFFEA00
sdramc_tr       MM	0xFFFFEA04
sdramc_cr       MM	0xFFFFEA08
sdramc_lpr      MM	0xFFFFEA10
sdramc_ier      MM	0xFFFFEA14
sdramc_idr      MM	0xFFFFEA18
sdramc_imr      MM	0xFFFFEA1C
sdramc_isr      MM	0xFFFFEA20
sdramc_mdr      MM	0xFFFFEA24
;
; Power Management Controller (PMC)
;
pmc_scer        MM	0xFFFFFC00
pmc_scdr        MM	0xFFFFFC04
pmc_scsr        MM	0xFFFFFC08
pmc_pcer        MM	0xFFFFFC10
pmc_pcdr        MM	0xFFFFFC14
pmc_pcsr        MM	0xFFFFFC18
ckgr_mor        MM	0xFFFFFC20
ckgr_mcfr       MM	0xFFFFFC24
ckgr_pllar      MM	0xFFFFFC28
ckgr_pllbr      MM	0xFFFFFC2C
pmc_mckr        MM	0xFFFFFC30
pmc_pck0        MM	0xFFFFFC40
pmc_pck1        MM	0xFFFFFC44
pmc_ier         MM	0xFFFFFC60
pmc_idr         MM	0xFFFFFC64
pmc_sr          MM	0xFFFFFC68
pmc_imr         MM	0xFFFFFC6C
pmc_pllicpr     MM	0xFFFFFC80
;
; Advanced Interrupt Controller (AIC)
;
aic_smr0        MM	0xFFFFF000	32      ;Source Mode Registers
aic_smr1        MM	0xFFFFF004	32
aic_smr2        MM	0xFFFFF008	32
aic_smr3        MM	0xFFFFF00C	32
aic_smr4        MM	0xFFFFF010	32
aic_smr5        MM	0xFFFFF014	32
aic_smr6        MM	0xFFFFF018	32
aic_smr7        MM	0xFFFFF01C	32
aic_smr8        MM	0xFFFFF020	32
aic_smr9        MM	0xFFFFF024	32
aic_smr10       MM	0xFFFFF028	32
aic_smr11       MM	0xFFFFF02C	32
aic_smr12       MM	0xFFFFF030	32
aic_smr13       MM	0xFFFFF034	32
aic_smr14       MM	0xFFFFF038	32
aic_smr15       MM	0xFFFFF03C	32
aic_smr16       MM	0xFFFFF040	32
aic_smr17       MM	0xFFFFF044	32
aic_smr18       MM	0xFFFFF048	32
aic_smr19       MM	0xFFFFF04C	32
aic_smr20       MM	0xFFFFF050	32
aic_smr21       MM	0xFFFFF054	32
aic_smr22       MM	0xFFFFF058	32
aic_smr23       MM	0xFFFFF05C	32
aic_smr24       MM	0xFFFFF060	32
aic_smr25       MM	0xFFFFF064	32
aic_smr26       MM	0xFFFFF068	32
aic_smr27       MM	0xFFFFF06C	32
aic_smr28       MM	0xFFFFF070	32
aic_smr29       MM	0xFFFFF074	32
aic_smr30       MM	0xFFFFF078	32
aic_smr31       MM	0xFFFFF07C	32
;
aic_svr0        MM	0xFFFFF080	32      ;Source Vector Registers
aic_svr1        MM	0xFFFFF084	32
aic_svr2        MM	0xFFFFF088	32
aic_svr3        MM	0xFFFFF08C	32
aic_svr4        MM	0xFFFFF090	32
aic_svr5        MM	0xFFFFF094	32
aic_svr6        MM	0xFFFFF098	32
aic_svr7        MM	0xFFFFF09C	32
aic_svr8        MM	0xFFFFF0A0	32
aic_svr9        MM	0xFFFFF0A4	32
aic_svr10       MM	0xFFFFF0A8	32
aic_svr11       MM	0xFFFFF0AC	32
aic_svr12       MM	0xFFFFF0B0	32
aic_svr13       MM	0xFFFFF0B4	32
aic_svr14       MM	0xFFFFF0B8	32
aic_svr15       MM	0xFFFFF0BC	32
aic_svr16       MM	0xFFFFF0C0	32
aic_svr17       MM	0xFFFFF0C4	32
aic_svr18       MM	0xFFFFF0C8	32
aic_svr19       MM	0xFFFFF0CC	32
aic_svr20       MM	0xFFFFF0D0	32
aic_svr21       MM	0xFFFFF0D4	32
aic_svr22       MM	0xFFFFF0D8	32
aic_svr23       MM	0xFFFFF0DC	32
aic_svr24       MM	0xFFFFF0E0	32
aic_svr25       MM	0xFFFFF0E4	32
aic_svr26       MM	0xFFFFF0E8	32
aic_svr27       MM	0xFFFFF0EC	32
aic_svr28       MM	0xFFFFF0F0	32
aic_svr29       MM	0xFFFFF0F4	32
aic_svr30       MM	0xFFFFF0F8	32
aic_svr31       MM	0xFFFFF0FC	32
;
aic_ivr         MM	0xFFFFF100	32      ;Interrupt Vector Register
aic_fvr         MM	0xFFFFF104	32      ;Fast Interrupt Vector Register
aic_isr         MM	0xFFFFF108	32      ;Interrupt Status Register
aic_ipr         MM	0xFFFFF10C	32      ;Interrupt Pending Register
aic_imr         MM	0xFFFFF110	32      ;Interrupt Mask Register
aic_cisr        MM	0xFFFFF114	32      ;Core Interrupt Status Register
aic_iecr        MM	0xFFFFF120	32      ;Interrupt Enable Command Register
aic_idcr        MM	0xFFFFF124	32      ;Interrupt Disable Command Register
aic_iccr        MM	0xFFFFF128	32      ;Interrupt Clear Command Register
aic_iscr        MM	0xFFFFF12C	32      ;Interrupt Set Command Register
aic_eoicr       MM	0xFFFFF130	32      ;End of Interrupt Command Register
aic_spu         MM	0xFFFFF134	32      ;Spurious Interrupt Vector Register
aic_dcr         MM	0xFFFFF138	32      ;Debug Control Register
aic_ffer        MM	0xFFFFF140	32      ;Fast Forcing Enable Register
aic_ffdr        MM	0xFFFFF144	32      ;Fast Forcing Disable Register
aic_ffsr        MM	0xFFFFF148	32      ;Fast Forcing Status Register
;
; Debug Unit (DBGU)
;
dbgu_cr         MM	0xFFFFF200	32      ;Control Register
dbgu_mr         MM	0xFFFFF204	32      ;Mode Register
dbgu_ier        MM	0xFFFFF208	32      ;Interrupt Enable Register
dbgu_idr        MM	0xFFFFF20C	32      ;Interrupt Disable Register
dbgu_imr        MM	0xFFFFF210	32      ;Interrupt Mask Register
dbgu_sr         MM	0xFFFFF214	32      ;Status Register
dbgu_rhr        MM	0xFFFFF218	32      ;Receive Holding Register
dbgu_thr        MM	0xFFFFF21C	32      ;Transmit Holding Register
dbgu_brgr       MM	0xFFFFF220	32      ;Baud Rate Generator Register
dbgu_cidr       MM	0xFFFFF240	32      ;Chip ID Register
dbgu_exid       MM	0xFFFFF244	32      ;Chip ID Extension Register
dbgu_fnr        MM	0xFFFFF248	32      ;Force NTRST Register
;
; Parallel Input/Output Controller (PIO)
;
pioa_per        MM	0xFFFFF400	32      ;PIO Enable Register
pioa_pdr        MM	0xFFFFF404	32      ;PIO Disable Register
pioa_psr        MM	0xFFFFF408	32      ;PIO Status Register (1)
pioa_oer        MM	0xFFFFF410	32      ;PIO Output Enable Register
pioa_odr        MM	0xFFFFF414	32      ;PIO Output Disable Register
pioa_osr        MM	0xFFFFF418	32      ;PIO Output Status Register
pioa_ifer       MM	0xFFFFF420	32      ;PIO Glitch Input Filter Enable Register
pioa_ifdr       MM	0xFFFFF424	32      ;PIO Glitch Input Filter Disable Register
pioa_ifsr       MM	0xFFFFF428	32      ;PIO Glitch Input Filter Status Register
pioa_sodr       MM	0xFFFFF430	32      ;PIO Set Output Data Register
pioa_codr       MM	0xFFFFF434	32      ;PIO Clear Output Data Register
pioa_odsr       MM	0xFFFFF438	32      ;PIO Output Data Status Register(2)
pioa_pdsr       MM	0xFFFFF43C	32      ;PIO Pin Data Status Register(3)
pioa_ier        MM	0xFFFFF440	32      ;PIO Interrupt Enable Register
pioa_idr        MM	0xFFFFF444	32      ;PIO Interrupt Disable Register
pioa_imr        MM	0xFFFFF448	32      ;PIO Interrupt Mask Register
pioa_isr        MM	0xFFFFF44C	32      ;PIO Interrupt Status Register(4)
pioa_mder       MM	0xFFFFF450	32      ;PIO Multi-driver Enable Register
pioa_mddr       MM	0xFFFFF454	32      ;PIO Multi-driver Disable Register
pioa_mdsr       MM	0xFFFFF458	32      ;PIO Multi-driver Status Register
pioa_pudr       MM	0xFFFFF460	32      ;PIO Pull-up Disable Register
pioa_puer       MM	0xFFFFF464	32      ;PIO Pull-up Enable Register
pioa_pusr       MM	0xFFFFF468	32      ;PIO Pad Pull-up Status Register
pioa_asr        MM	0xFFFFF470	32      ;PIO Peripheral A Select Register(5)
pioa_bsr        MM	0xFFFFF474	32      ;PIO Peripheral B Select Register(5)
pioa_absr       MM	0xFFFFF478	32      ;PIO AB Status Register(5)
pioa_ower       MM	0xFFFFF4A0	32      ;PIO Output Write Enable
pioa_owdr       MM	0xFFFFF4A4	32      ;PIO Output Write Disable
pioa_owsr       MM	0xFFFFF4A8	32      ;PIO Output Write Status Register
;
piob_per        MM	0xFFFFF600	32      ;PIOB
piob_pdr        MM	0xFFFFF604	32
piob_psr        MM	0xFFFFF608	32
piob_oer        MM	0xFFFFF610	32
piob_odr        MM	0xFFFFF614	32
piob_osr        MM	0xFFFFF618	32
piob_ifer       MM	0xFFFFF620	32
piob_ifdr       MM	0xFFFFF624	32
piob_ifsr       MM	0xFFFFF628	32
piob_sodr       MM	0xFFFFF630	32
piob_codr       MM	0xFFFFF634	32
piob_odsr       MM	0xFFFFF638	32
piob_pdsr       MM	0xFFFFF63C	32
piob_ier        MM	0xFFFFF640	32
piob_idr        MM	0xFFFFF644	32
piob_imr        MM	0xFFFFF648	32
piob_isr        MM	0xFFFFF64C	32
piob_mder       MM	0xFFFFF650	32
piob_mddr       MM	0xFFFFF654	32
piob_mdsr       MM	0xFFFFF658	32
piob_pudr       MM	0xFFFFF660	32
piob_puer       MM	0xFFFFF664	32
piob_pusr       MM	0xFFFFF668	32
piob_asr        MM	0xFFFFF670	32
piob_bsr        MM	0xFFFFF674	32
piob_absr       MM	0xFFFFF678	32
piob_ower       MM	0xFFFFF6A0	32
piob_owdr       MM	0xFFFFF6A4	32
piob_owsr       MM	0xFFFFF6A8	32
;
pioc_per        MM	0xFFFFF800	32      ;PIOC
pioc_pdr        MM	0xFFFFF804	32
pioc_psr        MM	0xFFFFF808	32
pioc_oer        MM	0xFFFFF810	32
pioc_odr        MM	0xFFFFF814	32
pioc_osr        MM	0xFFFFF818	32
pioc_ifer       MM	0xFFFFF820	32
pioc_ifdr       MM	0xFFFFF824	32
pioc_ifsr       MM	0xFFFFF828	32
pioc_sodr       MM	0xFFFFF830	32
pioc_codr       MM	0xFFFFF834	32
pioc_odsr       MM	0xFFFFF838	32
pioc_pdsr       MM	0xFFFFF83C	32
pioc_ier        MM	0xFFFFF840	32
pioc_idr        MM	0xFFFFF844	32
pioc_imr        MM	0xFFFFF848	32
pioc_isr        MM	0xFFFFF84C	32
pioc_mder       MM	0xFFFFF850	32
pioc_mddr       MM	0xFFFFF854	32
pioc_mdsr       MM	0xFFFFF858	32
pioc_pudr       MM	0xFFFFF860	32
pioc_puer       MM	0xFFFFF864	32
pioc_pusr       MM	0xFFFFF868	32
pioc_asr        MM	0xFFFFF870	32
pioc_bsr        MM	0xFFFFF874	32
pioc_absr       MM	0xFFFFF878	32
pioc_ower       MM	0xFFFFF8A0	32
pioc_owdr       MM	0xFFFFF8A4	32
pioc_owsr       MM	0xFFFFF8A8	32
;
; Serial Peripheral Interface (SPI)
;
spi0_cr         MM	0xFFFC8000	32      ;Control Register
spi0_mr         MM	0xFFFC8004	32      ;Mode Register
spi0_rdr        MM	0xFFFC8008	32      ;Receive Data Register
spi0_tdr        MM	0xFFFC800C	32      ;Transmit Data Register
spi0_sr         MM	0xFFFC8010	32      ;Status Register
spi0_ier        MM	0xFFFC8014	32      ;Interrupt Enable Register
spi0_idr        MM	0xFFFC8018	32      ;Interrupt Disable Register
spi0_imr        MM	0xFFFC801C	32      ;Interrupt Mask Register
spi0_csr0       MM	0xFFFC8030	32      ;Chip Select Register 0
spi0_csr1       MM	0xFFFC8034	32      ;Chip Select Register 1
spi0_csr2       MM	0xFFFC8038	32      ;Chip Select Register 2
spi0_csr3       MM	0xFFFC803C	32      ;Chip Select Register 3
;
spi1_cr         MM	0xFFFCC000	32      ;SPI1
spi1_mr         MM	0xFFFCC004	32
spi1_rdr        MM	0xFFFCC008	32
spi1_tdr        MM	0xFFFCC00C	32
spi1_sr         MM	0xFFFCC010	32
spi1_ier        MM	0xFFFCC014	32
spi1_idr        MM	0xFFFCC018	32
spi1_imr        MM	0xFFFCC01C	32
spi1_csr0       MM	0xFFFCC030	32
spi1_csr1       MM	0xFFFCC034	32
spi1_csr2       MM	0xFFFCC038	32
spi1_csr3       MM	0xFFFCC03C	32
;
; Two-wire Interface (TWI)
;
twi_cr          MM	0xFFFAC000	32      ;Control Register
twi_mmr         MM	0xFFFAC004	32      ;Master Mode Register
twi_iadr        MM	0xFFFAC00C	32      ;Internal Address Register
twi_cwgr        MM	0xFFFAC010	32      ;Clock Waveform Generator Register
twi_sr          MM	0xFFFAC020	32      ;Status Register
twi_ier         MM	0xFFFAC024	32      ;Interrupt Enable Register
twi_idr         MM	0xFFFAC028	32      ;Interrupt Disable Register
twi_imr         MM	0xFFFAC02C	32      ;Interrupt Mask Register
twi_rhr         MM	0xFFFAC030	32      ;Receive Holding Register
twi_thr         MM	0xFFFAC034	32      ;Transmit Holding Register
;
; USART (US)
;
us0_cr          MM	0xFFFB0000	32      ;Control Register
us0_mr          MM	0xFFFB0004	32      ;Mode Register
us0_ier         MM	0xFFFB0008	32      ;Interrupt Enable Register
us0_idr         MM	0xFFFB000C	32      ;Interrupt Disable Register
us0_imr         MM	0xFFFB0010	32      ;Interrupt Mask Register
us0_csr         MM	0xFFFB0014	32      ;Channel Status Register
us0_rhr         MM	0xFFFB0018	32      ;Receiver Holding Register
us0_thr         MM	0xFFFB001C	32      ;Transmitter Holding Register
us0_brgr        MM	0xFFFB0020	32      ;Baud Rate Generator Register
us0_rtor        MM	0xFFFB0024	32      ;Receiver Time-out Register
us0_ttgr        MM	0xFFFB0028	32      ;Transmitter Timeguard Register
us0_fidi        MM	0xFFFB0040	32      ;FI DI Ratio Register
us0_ner         MM	0xFFFB0044	32      ;Number of Errors Register
us0_if          MM	0xFFFB004C	32      ;IrDA Filter Register
;
us1_cr          MM	0xFFFB4000	32      ;USART1
us1_mr          MM	0xFFFB4004	32
us1_ier         MM	0xFFFB4008	32
us1_idr         MM	0xFFFB400C	32
us1_imr         MM	0xFFFB4010	32
us1_csr         MM	0xFFFB4014	32
us1_rhr         MM	0xFFFB4018	32
us1_thr         MM	0xFFFB401C	32
us1_brgr        MM	0xFFFB4020	32
us1_rtor        MM	0xFFFB4024	32
us1_ttgr        MM	0xFFFB4028	32
us1_fidi        MM	0xFFFB4040	32
us1_ner         MM	0xFFFB4044	32
us1_if          MM	0xFFFB404C	32
;
us2_cr          MM	0xFFFB8000	32      ;USART2
us2_mr          MM	0xFFFB8004	32
us2_ier         MM	0xFFFB8008	32
us2_idr         MM	0xFFFB800C	32
us2_imr         MM	0xFFFB8010	32
us2_csr         MM	0xFFFB8014	32
us2_rhr         MM	0xFFFB8018	32
us2_thr         MM	0xFFFB801C	32
us2_brgr        MM	0xFFFB8020	32
us2_rtor        MM	0xFFFB8024	32
us2_ttgr        MM	0xFFFB8028	32
us2_fidi        MM	0xFFFB8040	32
us2_ner         MM	0xFFFB8044	32
us2_if          MM	0xFFFB804C	32
;
; Serial Synchronous Controller (SSC)
;
ssc0_cr         MM	0xFFFBC000	32      ;Control Register
ssc0_cmr        MM	0xFFFBC004	32      ;Clock Mode Register
ssc0_rcmr       MM	0xFFFBC010	32      ;Receive Clock Mode Register
ssc0_rfmr       MM	0xFFFBC014	32      ;Receive Frame Mode Register
ssc0_tcmr       MM	0xFFFBC018	32      ;Transmit Clock Mode Register
ssc0_tfmr       MM	0xFFFBC01C	32      ;Transmit Frame Mode Register
ssc0_rhr        MM	0xFFFBC020	32      ;Receive Holding Register
ssc0_thr        MM	0xFFFBC024	32      ;Transmit Holding Register
ssc0_rshr       MM	0xFFFBC030	32      ;Receive Sync. Holding Register
ssc0_tshr       MM	0xFFFBC034	32      ;Transmit Sync. Holding Register
ssc0_sr         MM	0xFFFBC040	32      ;Status Register
ssc0_ier        MM	0xFFFBC044	32      ;Interrupt Enable Register
ssc0_idr        MM	0xFFFBC048	32      ;Interrupt Disable Register
ssc0_imr        MM	0xFFFBC04C	32      ;Interrupt Mask Register
;
ssc1_cr         MM	0xFFFC0000	32      ;SSC1
ssc1_cmr        MM	0xFFFC0004	32
ssc1_rcmr       MM	0xFFFC0010	32
ssc1_rfmr       MM	0xFFFC0014	32
ssc1_tcmr       MM	0xFFFC0018	32
ssc1_tfmr       MM	0xFFFC001C	32
ssc1_rhr        MM	0xFFFC0020	32
ssc1_thr        MM	0xFFFC0024	32
ssc1_rshr       MM	0xFFFC0030	32
ssc1_tshr       MM	0xFFFC0034	32
ssc1_sr         MM	0xFFFC0040	32
ssc1_ier        MM	0xFFFC0044	32
ssc1_idr        MM	0xFFFC0048	32
ssc1_imr        MM	0xFFFC004C	32
;
ssc2_cr         MM	0xFFFC4000	32      ;SSC2
ssc2_cmr        MM	0xFFFC4004	32
ssc2_rcmr       MM	0xFFFC4010	32
ssc2_rfmr       MM	0xFFFC4014	32
ssc2_tcmr       MM	0xFFFC4018	32
ssc2_tfmr       MM	0xFFFC401C	32
ssc2_rhr        MM	0xFFFC4020	32
ssc2_thr        MM	0xFFFC4024	32
ssc2_rshr       MM	0xFFFC4030	32
ssc2_tshr       MM	0xFFFC4034	32
ssc2_sr         MM	0xFFFC4040	32
ssc2_ier        MM	0xFFFC4044	32
ssc2_idr        MM	0xFFFC4048	32
ssc2_imr        MM	0xFFFC404C	32
;
; Timer Counter 0,1,2 (TC)
;
tc0_ccr         MM	0xFFFA0000	32      ;Channel Control Register
tc0_cmr         MM	0xFFFA0004	32      ;Channel Mode Register
tc0_cv          MM	0xFFFA0010	32      ;Counter Value
tc0_ra          MM	0xFFFA0014	32      ;Register A
tc0_rb          MM	0xFFFA0018	32      ;Register B
tc0_rc          MM	0xFFFA001C	32      ;Register C
tc0_sr          MM	0xFFFA0020	32      ;Status Register
tc0_ier         MM	0xFFFA0024	32      ;Interrupt Enable Register
tc0_idr         MM	0xFFFA0028	32      ;Interrupt Disable Register
tc0_imr         MM	0xFFFA002C	32      ;Interrupt Mask Register
;
tc1_ccr         MM	0xFFFA0040	32      ;TC1
tc1_cmr         MM	0xFFFA0044	32
tc1_cv          MM	0xFFFA0050	32
tc1_ra          MM	0xFFFA0054	32
tc1_rb          MM	0xFFFA0058	32
tc1_rc          MM	0xFFFA005C	32
tc1_sr          MM	0xFFFA0060	32
tc1_ier         MM	0xFFFA0064	32
tc1_idr         MM	0xFFFA0068	32
tc1_imr         MM	0xFFFA006C	32
;
tc2_ccr         MM	0xFFFA0080	32      ;TC2
tc2_cmr         MM	0xFFFA0084	32
tc2_cv          MM	0xFFFA0090	32
tc2_ra          MM	0xFFFA0094	32
tc2_rb          MM	0xFFFA0098	32
tc2_rc          MM	0xFFFA009C	32
tc2_sr          MM	0xFFFA00A0	32
tc2_ier         MM	0xFFFA00A4	32
tc2_idr         MM	0xFFFA00A8	32
tc2_imr         MM	0xFFFA00AC	32
;
tc0_bcr         MM	0xFFFA00C0	32      ;Block Control Register
tc0_bmr         MM	0xFFFA00C4	32      ;Block Mode Register
;
; MultiMedia Card (MCI)
;
mci_cr          MM	0xFFFA8000	32      ;Control Register
mci_mr          MM	0xFFFA8004	32      ;Mode Register
mci_dtor        MM	0xFFFA8008	32      ;Data Timeout Register
mci_sdcr        MM	0xFFFA800C	32      ;SD Card Register
mci_argr        MM	0xFFFA8010	32      ;Argument Register
mci_cmdr        MM	0xFFFA8014	32      ;Command Register
mci_rspr        MM	0xFFFA8020	32      ;Response Register
mci_rdr         MM	0xFFFA8030	32      ;Receive Data Register
mci_tdr         MM	0xFFFA8034	32      ;Transmit Data Register
mci_sr          MM	0xFFFA8040	32      ;Status Register
mci_ier         MM	0xFFFA8044	32      ;Interrupt Enable Register
mci_idr         MM	0xFFFA8048	32      ;Interrupt Disable Register
mci_imr         MM	0xFFFA804C	32      ;Interrupt Mask Register
;