;Register definition for Marvell 88F6281
;=======================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
;  Register Numbers for Fero926:
;  +-------+-------+-------+-------+
;  | | | | | | | | | | | | | | | | |
;  +-+-----+-+-----+-------+-------+
;  |-|opc_1|-|opc_2|  CRm  |  nbr  |
;  +-+-----+-+-----+-------+-------+
;
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x0100          32      ;Cache type
tcm             CP15    0x0200          32      ;TCM status
control 	CP15    0x0001          32      ;Control
ttb     	CP15    0x0002          32      ;Translation table base
dac     	CP15    0x0003          32      ;Domain access control
dfsr      	CP15    0x0005          32      ;Data fault status
ifsr    	CP15    0x0105          32      ;Inst fault status
far       	CP15    0x0006          32      ;Fault address
;
fcsr      	CP15    0x000d          32      ;Fast context switch PID
context 	CP15    0x010d          32      ;Context ID
;
;
;       DDR SDRAM Controller Registers
;
ddr_cpuw0_base  DMM1    0x01500
ddr_cpuw0_size  DMM1    0x01504
ddr_cpuw1_base  DMM1    0x01508
ddr_cpuw1_size  DMM1    0x0150C
ddr_cpuw2_base  DMM1    0x01510
ddr_cpuw2_size  DMM1    0x01514
ddr_cpuw3_base  DMM1    0x01518
ddr_cpuw3_size  DMM1    0x0151C
;
ddr_config      DMM1    0x01400
ddr_ctrl_low    DMM1    0x01404
ddr_timing_lo   DMM1    0x01408
ddr_timing_hi   DMM1    0x0140C
ddr_addr_ctrl   DMM1    0x01410
ddr_open_page   DMM1    0x01414
ddr_operation   DMM1    0x01418
ddr_mode        DMM1    0x0141C
ddr_xmode       DMM1    0x01420
ddr_ctrl_high   DMM1    0x01424
ddr2_timing_lo  DMM1    0x01428
ddr_op_ctrl     DMM1    0x0142C
ddr_mbus_ctr_lo DMM1    0x01430
ddr_mbus_ctr_hi DMM1    0x01434
ddr_mbus_timing DMM1    0x01438
ddr2_timing_hi  DMM1    0x0147C
ddr_init_ctrl   DMM1    0x01480
ddr_xmode2      DMM1    0x0148C
ddr_xmode3      DMM1    0x01490
ddr_odt_ctr_lo  DMM1    0x01494
ddr_odt_ctr_hi  DMM1    0x01498
ddr_odt_control DMM1    0x0149C
ddr_rbuf_select DMM1    0x014A4
ddr_ad_pads     DMM1    0x014C0
ddr_dq_pads     DMM1    0x014C4
ddr_dqs_pads    DMM1    0x014C8
;
;       MPP Registers
;
mpp_control0    DMM1    0x10000
mpp_control1    DMM1    0x10004
mpp_control2    DMM1    0x10008
mpp_control3    DMM1    0x1000C
mpp_control4    DMM1    0x10014
mpp_control5    DMM1    0x10018
mpp_control6    DMM1    0x1001C
mpp_reset_cfg   DMM1    0x10030
;