; bdiGDB configuration for Marvell OpenRD board ; --------------------------------------------- ; ; Info about the JTAG clock frequency: ; ------------------------------------ ; BDI2000: ; 0=Adaptive, ; 1=16MHz, 2=8MHz, 3=4MHz, ; 4= 1MHz, 5=500kHz, 6=200kHz, 7=100kHz, 8=50kHz, ; 9=20kHz, 10=10kHz, 11=5kHz, 12=2kHz, 13=1kHz ; BDI3000: ; 0=Adaptive, ; 1=32MHz, 2=16MHz, 3=11MHz, 4=8MHz, 5=5MHz, 6=4MHz, ; 7=1MHz, 8=500kHz, 9=200kHz, 10=100kHz, 11=50kHz, ; 12=20kHz, 13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz, ; ; ; [INIT] ; WCP15 0x0001 0x00052078 ;Control: ; WM32 0xD0001400 0x43000C30 ;DDR SDRAM Configuration Register WM32 0xD0001404 0x37543000 ;Dunit Control Low Register WM32 0xD0001408 0x22125451 ;DDR SDRAM Timing (Low) Register WM32 0xD000140C 0x00000A33 ;DDR SDRAM Timing (High) Register WM32 0xD0001410 0x000000CC ;DDR SDRAM Address Control Register WM32 0xD0001414 0x00000000 ;DDR SDRAM Open Pages Control Register WM32 0xD0001418 0x00000000 ;DDR SDRAM Operation Register WM32 0xD000141C 0x00000C52 ;DDR SDRAM Mode Register WM32 0xD0001420 0x00000004 ;DDR SDRAM Extended Mode Register WM32 0xD0001424 0x0000F17F ;Dunit Control High Register WM32 0xD0001428 0x00085520 ;Dunit Control High Register WM32 0xD000147c 0x00008552 ;Dunit Control High Register WM32 0xD0001504 0x0FFFFFF1 ;CS0n Size Register WM32 0xD0001508 0x10000000 ;CS1n Base Register WM32 0xD000150C 0x0FFFFFF5 ;CS1n Size Register WM32 0xD0001514 0x00000000 ;CS2n Size Register WM32 0xD000151C 0x00000000 ;CS3n Size Register WM32 0xD0001494 0x00120012 ;DDR2 SDRAM ODT Control (Low) Register WM32 0xD0001498 0x00000000 ;DDR2 SDRAM ODT Control (High) REgister WM32 0xD000149C 0x0000E40F ;DDR2 Dunit ODT Control Register WM32 0xD0001480 0x00000001 ;DDR SDRAM Initialization Control Register DELAY 100 ;give DDR time to initialize ; WM32 0xD0010000 0x11111111 ;MPP 0 to 7 WM32 0xD0010004 0x00000000 ;MPP 8 to 15 WM32 0xD0010008 0x00001100 ;MPP 16 to 23 ; [TARGET] CPUTYPE FERO926 CLOCK 1 4 ;BDI2000: start with 1 MHz then use 16 MHz TRST PUSHPULL ;TRST driver type (OPENDRAIN | PUSHPULL) POWERUP 2000 WAKEUP 500 RESET HARD 500 ;NONE | HARD (ms) STARTUP RESET ENDIAN LITTLE ;memory model (LITTLE | BIG) BREAKMODE SOFT ;Use ARM9E BKPT instruction STEPMODE HWBP ;FEROCEON supports only HWBP single step VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset [HOST] IP 151.120.25.119 FILE E:\temp\dump16k.bin FORMAT BIN 0x00010000 PROMPT OpenRD> [FLASH] [REGS] DMM1 0xD0000000 ;Internal Address Space FILE $reg88F6281.def