; bdiGDB configuration for Motorola M9328MX1ADS board ; --------------------------------------------------- ; [INIT] ; ; Initialize DragonBall MX1 ADS Rev 0.1 board when using JTAG ; so SRAM and SDRAM are downloadable ; WM32 0x0021b000 0x2f00ac03 ;Select CLKO mux to output HCLK(BCLK) WM32 0x0021b000 0x2f008403 ;48MHz System Clock WM32 0x00220000 0x00002000 ;CS0 - boot flash, 32 wait states, 8-bit WM32 0x00220004 0x11110301 WM32 0x00220008 0x00000a00 ;CS1 - SRAM, 10 wait states, 32-bit WM32 0x0022000c 0x11110601 WM32 0x00220020 0x00000a00 ;CS4 - External UART, 10 wait states, 8-bit WM32 0x00220024 0x11110301 ; ;Init SDRAM 16Mx16x2 IAM0 CS2 CL2 ; WM32 0x00221000 0x92120200 ;Set Precharge Command WM32 0x08200000 0x00000000 ;Issue Precharge all Command WM32 0x00221000 0xa2120200 ;Set AutoRefresh Command WM32 0x08000000 0x00000000 ;Issue AutoRefresh Command WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x08000000 0x00000000 WM32 0x00221000 0xb2120200 ;Set Mode Register WM32 0x08111800 0x00000000 ;Issue Mode Register Command, Burst Length = 8 WM32 0x00221000 0x82124200 ;Set to Normal Mode ; [TARGET] CPUTYPE ARM920T CLOCK 1 ;JTAG clock (0=Adaptive, 1=8MHz, 2=4MHz, 3=2MHz) WAKEUP 3000 ;because of slow rising reset line RESET HARD 1000 ;beause of heavy capacitive load on reset line ENDIAN LITTLE ;memory model (LITTLE | BIG) BREAKMODE SOFT 0xDFFFDFFF ;SOFT or HARD, ARM / Thumb break code ;VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset ;SIO 7 9600 ;TCP port for serial IO ;DCC 7 ;TCP port for DCC I/O [HOST] IP 151.120.25.119 ;FILE E:\cygwin\home\bdidemo\arm\vxworks ;FORMAT BIN 0x12000000 FILE E:\cygwin\home\demo\mx1\fibo.x FORMAT ELF LOAD MANUAL ;load VxWorks code MANUAL or AUTO after reset [FLASH] [REGS] FILE E:\cygwin\home\bdidemo\arm\regMX1.def