; bdiGDB configuration for Marvell Feroceon ARM966 (Dragonite) ; ------------------------------------------------------------ ; ; Commands supported in the SCANINIT and SCANPOST strings: ; ; I=<...b2b1b0> write IR, b0 is first scanned ; D=<...b2b1b0> write DR, b0 is first scanned ; n : the number of bits 1..256 ; bx : a data byte, two hex digits ; W wait for n (decimal) micro seconds ; T1 assert TRST ; T0 release TRST ; R1 assert RESET ; R0 release RESET ; CH clock TCK n (decimal) times with TMS high ; CL clock TCK n (decimal) times with TMS low ; ; [INIT] ; ;WGPR 11 0x00000020 ;set frame pointer to free RAM ;WM32 0x00000020 0x00000028 ;dummy stack frame ; ;MMAP 0x00000000 0x01FFFFFF ;enable access to SDRAM ; [TARGET] CPUTYPE FERO966 ;CLOCK 0 4 ;JTAG clock : start with 500 kHz then use adaptive CLOCK 4 ;JTAG clock : without adaptive clocking cable POWERUP 20000 ;time to load FPGA (20 sec) TRST OPENDRAIN ;TRST driver type (OPENDRAIN | PUSHPULL) RESET HARD 500 ;NONE | HARD (ms) STARTUP RESET ENDIAN LITTLE ;memory model (LITTLE | BIG) BREAKMODE SOFT ;Use ARM9E BKPT instruction ;STEPMODE HWBP ;FEROCEON supports only HWBP single step VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset WAKEUP 10000 ;DCC 7 ;DCC I/O via TCP port 7 SCANPRED 0 0 ;no device before ARM966 SCANSUCC 1 4 ;count for ???? ;SCANINIT r1:w100000:r0:w1000 ;toggle RESET ;SCANPOST r1:w100000:r0:w1000 ;toggle RESET [HOST] IP 151.120.25.119 FILE E:\temp\dump16k.bin FORMAT BIN 0x00010000 PROMPT FERO966> [FLASH] ; only to test DCC communication WORKSPACE 0x00001000 ;workspace at 0x1000 CHIPTYPE AM29BX16 CHIPSIZE 0x100000 BUSWIDTH 16 FILE E:/temp/dump128k.bin FORMAT BIN 0x110000 [REGS] FILE $regFero966.def