; bdiGDB configuration for Marvell Feroceon ARM926 (Mohawk)
; ---------------------------------------------------------
;
;
[INIT]
;
;Setup MMU and enable cache, Translation table at 0x00004000
;
WCP15   0x0002      0x00004000  ;set Translation Base Address
WCP15   0x0003      0xFFFFFFFF  ;set Domain Access Control
WM32    0x00004000  0x00000C0E  ;MMU: 0x00000000, cacheable, bufferable
WM32    0x00004004  0x00100C0E  ;MMU: 0x00100000, cacheable, bufferable
WM32    0x00004008  0x00200C0E  ;MMU: 0x00200000, cacheable, bufferable
WM32    0x0000400C  0x00300C0E  ;MMU: 0x00300000, cacheable, bufferable
WM32    0x00004010  0x00400C0E  ;MMU: 0x00400000, cacheable, bufferable
WM32    0x00004014  0x00500C0E  ;MMU: 0x00500000, cacheable, bufferable
WM32    0x00004018  0x00600C0E  ;MMU: 0x00600000, cacheable, bufferable
WM32    0x0000401C  0x00700C0E  ;MMU: 0x00700000, cacheable, bufferable
WM32    0x00004020  0x00800C0E  ;MMU: 0x00800000, cacheable, bufferable
WM32    0x00004024  0x00900C0E  ;MMU: 0x00900000, cacheable, bufferable
WM32    0x00004028  0x00A00C0E  ;MMU: 0x00A00000, cacheable, bufferable
WM32    0x0000402C  0x00B00C0E  ;MMU: 0x00B00000, cacheable, bufferable
WM32    0x00004030  0x00C00C0E  ;MMU: 0x00C00000, cacheable, bufferable
WM32    0x00004034  0x00D00C0E  ;MMU: 0x00D00000, cacheable, bufferable
WM32    0x00004038  0x00E00C0E  ;MMU: 0x00E00000, cacheable, bufferable
WM32    0x0000403C  0x00F00C0E  ;MMU: 0x00F00000, cacheable, bufferable
;
WCP15   0x0001     0x0005107D  ;enable MMU , Caches and Write Buffer
;
WREG    CPSR        0x000000d3  ;set superviser mode
WGPR    15          0x00000000  ;set PC = 0
WGPR    11          0x00000020  ;set frame pointer to free RAM
WM32    0x00000020  0x00000028	;dummy stack frame
;
MMAP    0x00000000  0x00FFFFFF  ;enable access to mapped SDRAM
;


[TARGET]
CPUTYPE     FERO926
;CLOCK       0 4                 ;JTAG clock : start with 500 kHz then use adaptive
CLOCK       4                   ;JTAG clock : without adaptive clocking cable
POWERUP     20000               ;time to load FPGA (20 sec)
TRST        OPENDRAIN           ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	    HARD 500            ;NONE | HARD <n> (ms)
STARTUP     RESET
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;Use ARM9E BKPT instruction
STEPMODE    HWBP                ;FEROCEON supports only HWBP single step
WAKEUP      10000

SCANINIT    r1:w100000:r0:w1000         ;toggle RESET

;SCANPOST    r1:w100000:r0:w1000         ;toggle RESET


[HOST]
IP          151.120.25.119
FILE        E:\temp\dump16k.bin
FORMAT      BIN  0x00010000
PROMPT      FERO926>


[FLASH]

[REGS]
FILE	$regFero926.def