;Register definition for STM32
;=============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
;name		type	addr		size
;-------------------------------------------
;
sp_main         GPR     17              32      ;Main Stackpointer
sp_process      GPR     18              32      ;Process Stackpointer
ctr_fm_bp_pm	GPR	20	32	;Control,FaultMask,BasePri,PriMask
;
; Core debug registres
dhcsr           MM      0xE000EDF0      32      ;Debugging Halting Control and Status
dcrsr           MM      0xE000EDF4      32      ;Debug Core Register Selector
dcrdr           MM      0xE000EDF8      32      ;Debug Core Register Data
demcr           MM      0xE000EDFC      32      ;Debug Core Register Selector
dfsr            MM      0xE000ED30      32      ;Debug Fault Status
;
; System debug registers
fp_ctrl         MM      0xE0002000      32      ;Flash Patch Control
fp_remap        MM      0xE0002004      32      ;Flash Patch Remap
fp_comp0        MM      0xE0002008      32      ;Flash Patch Comparator
fp_comp1        MM      0xE000200C      32      ;Flash Patch Comparator
fp_comp2        MM      0xE0002010      32      ;Flash Patch Comparator
fp_comp3        MM      0xE0002014      32      ;Flash Patch Comparator
fp_comp4        MM      0xE0002018      32      ;Flash Patch Comparator
fp_comp5        MM      0xE000201C      32      ;Flash Patch Comparator
fp_comp6        MM      0xE0002020      32      ;Flash Patch Comparator
fp_comp7        MM      0xE0002024      32      ;Flash Patch Comparator
;
dwt_ctrl        MM      0xE0001000      32      ;DWT Control
dwt_cyccnt      MM      0xE0001004      32      ;DWT Current PC Sampler Count
dwt_cpicnt      MM      0xE0001008      32      ;DWT Current CPI Count
dwt_exccnt      MM      0xE000100C      32      ;DWT Current Interrupt Overhead Count
dwt_sleepcnt    MM      0xE0001010      32      ;DWT Current Sleep Count
dwt_lsucnt      MM      0xE0001014      32      ;DWT Current LSU Count
dwt_foldcnt     MM      0xE0001018      32      ;DWT Current Fold Count
dwt_pcsr        MM      0xE000101C      32      ;DWT PC Sample
dwt_comp0       MM      0xE0001020      32      ;DWT Comparator
dwt_mask0       MM      0xE0001024      32      ;DWT Mask
dwt_function0   MM      0xE0001028      32      ;DWT Function
dwt_comp1       MM      0xE0001030      32      ;DWT Comparator
dwt_mask1       MM      0xE0001034      32      ;DWT Mask
dwt_function1   MM      0xE0001038      32      ;DWT Function
dwt_comp2       MM      0xE0001040      32      ;DWT Comparator
dwt_mask2       MM      0xE0001044      32      ;DWT Mask
dwt_function2   MM      0xE0001048      32      ;DWT Function
dwt_comp3       MM      0xE0001050      32      ;DWT Comparator
dwt_mask3       MM      0xE0001054      32      ;DWT Mask
dwt_function3   MM      0xE0001058      32      ;DWT Function
;
; Debug support (DBG)
dbgmcu_idcode   MM      0xE0042000      32      ;MCU device ID code
dbgmcu_cr       MM      0xE0042004      32      ;Debug MCU configuration
dbgmcu_apb1_fz  MM      0xE0042008      32      ;Debug MCU APB1 freeze
dbgmcu_apb2_fz  MM      0xE004200c      32      ;Debug MCU APB2 freeze
;
; Flash registers
flash_acr       MM      0x40023c00      32      ;Flash Access Control
flash_pecr      MM      0x40023c04      32      ;Flash Access Control
flash_pdkeyr    MM      0x40023c08      32      ;Flash Access Control
flash_pekeyr    MM      0x40023c0c      32      ;Flash Access Control
flash_prgkeyr   MM      0x40023c10      32      ;Flash Access Control
flash_optkeyr   MM      0x40023c14      32      ;Flash Option Key
flash_sr        MM      0x40023c18      32      ;Flash Status
flash_obr       MM      0x40023c1C      32      ;Flash Option Byte
flash_wrpr      MM      0x40023c20      32      ;Flash Write Protection
;
; Reset and clock control (RCC)
rcc_cr          MM      0x40023800      32      ;Clock control
rcc_icscr       MM      0x40023804      32      ;Internal clock sources calibration
rcc_cfgr        MM      0x40023808      32      ;Clock configuration
rcc_cir         MM      0x4002380c      32      ;Clock interrupt
rcc_ahbrstr     MM      0x40023810      32      ;AHB peripheral reset
rcc_apb2rstr    MM      0x40023814      32      ;APB2 peripheral reset
rcc_apb1rstr    MM      0x40023818      32      ;APB1 peripheral reset
rcc_ahbenr      MM      0x4002381c      32      ;AHB peripheral clock enable
rcc_apb2enr     MM      0x40023820      32      ;APB2 peripheral clock enable
rcc_apb1enr     MM      0x40023824      32      ;APB1 peripheral clock enable
rcc_ahblpenr    MM      0x40023828      32      ;AHB peripheral clock enable in low power mode
rcc_apb2lpenr   MM      0x4002382c      32      ;APB2 peripheral clock enable in low power mode
rcc_apb1lpenr   MM      0x40023830      32      ;APB1 peripheral clock enable in low power mode
rcc_csr         MM      0x40023834      32      ;Control/status
;
; System configuration controller (SYSCFG)
syscfg_memrmp   MM      0x40010000      32      ;SYSCFG memory remap
syscfg_pmc      MM      0x40010004      32      ;SYSCFG peripheral mode configuration
syscfg_exticr1  MM      0x40010008      32      ;SYSCFG external interrupt configuration 1
syscfg_exticr2  MM      0x4001000c      32      ;SYSCFG external interrupt configuration 2
syscfg_exticr3  MM      0x40010010      32      ;SYSCFG external interrupt configuration 3
syscfg_exticr4  MM      0x40010014      32      ;SYSCFG external interrupt configuration 4
;
; Power control (PWR)
pwr_cr          MM      0x40007000      32      ;PWR power control
pwr_csr         MM      0x40007004      32      ;PWR power control/status
;

