;Register definition for Atmel AT91SAM3U ;======================================= ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ; ;name type addr size ;------------------------------------------- ; sp_main GPR 17 32 ;Main Stackpointer sp_process GPR 18 32 ;Process Stackpointer ctr_fm_bp_pm GPR 20 32 ;Control,FaultMask,BasePri,PriMask ; ; Core debug registres dhcsr MM 0xE000EDF0 32 ;Debugging Halting Control and Status dcrsr MM 0xE000EDF4 32 ;Debug Core Register Selector dcrdr MM 0xE000EDF8 32 ;Debug Core Register Data demcr MM 0xE000EDFC 32 ;Debug Core Register Selector dfsr MM 0xE000ED30 32 ;Debug Fault Status ; ; System debug registres fp_ctrl MM 0xE0002000 32 ;Flash Patch Control fp_remap MM 0xE0002004 32 ;Flash Patch Remap fp_comp0 MM 0xE0002008 32 ;Flash Patch Comparator fp_comp1 MM 0xE000200C 32 ;Flash Patch Comparator fp_comp2 MM 0xE0002010 32 ;Flash Patch Comparator fp_comp3 MM 0xE0002014 32 ;Flash Patch Comparator fp_comp4 MM 0xE0002018 32 ;Flash Patch Comparator fp_comp5 MM 0xE000201C 32 ;Flash Patch Comparator fp_comp6 MM 0xE0002020 32 ;Flash Patch Comparator fp_comp7 MM 0xE0002024 32 ;Flash Patch Comparator ; dwt_ctrl MM 0xE0001000 32 ;DWT Control dwt_cyccnt MM 0xE0001004 32 ;DWT Current PC Sampler Count dwt_cpicnt MM 0xE0001008 32 ;DWT Current CPI Count dwt_exccnt MM 0xE000100C 32 ;DWT Current Interrupt Overhead Count dwt_sleepcnt MM 0xE0001010 32 ;DWT Current Sleep Count dwt_lsucnt MM 0xE0001014 32 ;DWT Current LSU Count dwt_foldcnt MM 0xE0001018 32 ;DWT Current Fold Count dwt_pcsr MM 0xE000101C 32 ;DWT PC Sample dwt_comp0 MM 0xE0001020 32 ;DWT Comparator dwt_mask0 MM 0xE0001024 32 ;DWT Mask dwt_function0 MM 0xE0001028 32 ;DWT Function dwt_comp1 MM 0xE0001030 32 ;DWT Comparator dwt_mask1 MM 0xE0001034 32 ;DWT Mask dwt_function1 MM 0xE0001038 32 ;DWT Function dwt_comp2 MM 0xE0001040 32 ;DWT Comparator dwt_mask2 MM 0xE0001044 32 ;DWT Mask dwt_function2 MM 0xE0001048 32 ;DWT Function dwt_comp3 MM 0xE0001050 32 ;DWT Comparator dwt_mask3 MM 0xE0001054 32 ;DWT Mask dwt_function3 MM 0xE0001058 32 ;DWT Function ; ; ; Embedded Flash Controller ; eefc0_fmr MM 0x400E0800 32 eefc0_fcr MM 0x400E0804 32 eefc0_fsr MM 0x400E0808 32 eefc0_frr MM 0x400E080C 32 ; eefc1_fmr MM 0x400E0A00 32 eefc1_fcr MM 0x400E0A04 32 eefc1_fsr MM 0x400E0A08 32 eefc1_frr MM 0x400E0A0C 32 ; ; Watchdog Timer ; wdt_cr MM 0x400E1250 32 wdt_mr MM 0x400E1254 32 wdt_sr MM 0x400E1258 32 ; ; Reset Controller ; rstc_cr MM 0x400E1200 32 rstc_sr MM 0x400E1204 32 rstc_mr MM 0x400E1208 32 ; ; Power Management Controller ; pmc_scer MM 0x400E0400 32 pmc_scdr MM 0x400E0404 32 pmc_scsr MM 0x400E0408 32 pmc_pcer MM 0x400E0410 32 pmc_pcdr MM 0x400E0414 32 pmc_pcsr MM 0x400E0418 32 ckgr_uckr MM 0x400E041C 32 ckgr_mor MM 0x400E0420 32 ckgr_mcfr MM 0x400E0424 32 ckgr_pllar MM 0x400E0428 32 pmc_mckr MM 0x400E0430 32 pmc_pck0 MM 0x400E0440 32 pmc_pck1 MM 0x400E0444 32 pmc_pck2 MM 0x400E0448 32 pmc_ier MM 0x400E0460 32 pmc_idr MM 0x400E0464 32 pmc_sr MM 0x400E0468 32 pmc_imr MM 0x400E046C 32 pmc_fsmr MM 0x400E0470 32 pmc_fspr MM 0x400E0474 32 pmc_focr MM 0x400E0478 32 pmc_wpmr MM 0x400E04E4 32 pmc_wpsr MM 0x400E04E8 32 ;