;Register definition for ARM1176
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CPx	CPx register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CPx Registers Numbers for ARM11 cores:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
mainid		CP15    0x0000          32      ;ID code
cachetype   	CP15    0x2000          32      ;Cache type
tcmstatus       CP15    0x4000          32      ;TCM status
tlbtype         CP15    0x6000          32      ;TCM type
;
procfeature0    CP15    0x0100          32      ;Processor Feature 0
procfeature1    CP15    0x2100          32      ;Processor Feature 1
dbgfeature0     CP15    0x4100          32      ;Debug Feature 0
auxfeature0     CP15    0x6100          32      ;Auxiliary Feature 0
memfeature0     CP15    0x8100          32      ;Memory Model Feature 0
memfeature1     CP15    0xa100          32      ;Memory Model Feature 1
memfeature2     CP15    0xc100          32      ;Memory Model Feature 2
memfeature3     CP15    0xe100          32      ;Memory Model Feature 3
;
instrattr0      CP15    0x0200          32      ;Instruction Set Attribute 0
instrattr1      CP15    0x2200          32      ;Instruction Set Attribute 1
instrattr2      CP15    0x4200          32      ;Instruction Set Attribute 2
instrattr3      CP15    0x6200          32      ;Instruction Set Attribute 3
instrattr4      CP15    0x8200          32      ;Instruction Set Attribute 4
instrattr5      CP15    0xa200          32      ;Instruction Set Attribute 5
;
control         CP15    0x0001          32      ;Control
auxcontrol     	CP15    0x2001          32      ;Auxiliary Control
cpaccess   	CP15    0x4001          32      ;Coprocessor Access
;
securecfg       CP15    0x0101          32      ;Secure Configuration
securedbg       CP15    0x2101          32      ;Secure Debug Enable
nonsecure       CP15    0x4101          32      ;Nonsecure Access Control
;
ttb0            CP15    0x0002          32      ;Translation Table Base 0
ttb1            CP15    0x2002          32      ;Translation Table Base 1
ttbc            CP15    0x4002          32      ;Translation Table Base Control
;
dac             CP15    0x0003          32      ;Domain Access Control
;
dfsr     	CP15    0x0005          32      ;Data Fault Status
ifsr     	CP15    0x2005          32      ;Instruction Fault Status
;
far     	CP15    0x0006          32      ;Fault Address
wfar     	CP15    0x2006          32      ;Watchpoint  Fault Address
ifar     	CP15    0x2006          32      ;Instruction Fault Address
;
fcsepid        	CP15    0x000d          32      ;Process ID
context        	CP15    0x200d          32      ;Context ID
;
;
; Debug Registers
;
didr       	CP14    0x0000          32      ;Debug ID
dscr       	CP14    0x0100          32      ;Debug Status and Control
;dtr        	CP14    0x0500          32      ;Data Transfer
wfar       	CP14    0x0600          32      ;Watchpoint Fault Address
vcr        	CP14    0x0700          32      ;Vector Catch
dsccr      	CP14    0x0a00          32      ;Debug State Cache Control
dsmcr      	CP14    0x0b00          32      ;Debug State MMU Control
;
bvr0       	CP14    0x8000          32      ;Breakpoint value
bvr1       	CP14    0x8100          32
bvr2       	CP14    0x8200          32
bvr3       	CP14    0x8300          32
bvr4       	CP14    0x8400          32
bvr5       	CP14    0x8500          32
;
wvr0       	CP14    0xc000          32      ;Watchpoint value
wvr1       	CP14    0xc100          32
;
;
; Memory Mapped Registres
; =======================
;
; SYSTEM Cotroller
;
apll_lock       MM      0x7E00F000
mpll_lock       MM      0x7E00F004
epll_lock       MM      0x7E00F008
apll_con        MM      0x7E00F00C
mpll_con        MM      0x7E00F010
epll_con0       MM      0x7E00F014
epll_con1       MM      0x7E00F018
clk_src         MM      0x7E00F01C
clk_div0        MM      0x7E00F020
clk_div1        MM      0x7E00F024
clk_div2        MM      0x7E00F028
clk_out         MM      0x7E00F02C
hclk_gate       MM      0x7E00F030
pclk_gate       MM      0x7E00F034
sclk_gate       MM      0x7E00F038
ahb_con0        MM      0x7E00F100
ahb_con1        MM      0x7E00F104
ahb_con2        MM      0x7E00F108
sdma_sel        MM      0x7E00F110
sw_rst          MM      0x7E00F114
sys_id          MM      0x7E00F118
mem_sys_cfg     MM      0x7E00F120
qos_override0   MM      0x7E00F124
qos_override1   MM      0x7E00F128
mem_cfg_stat    MM      0x7E00F12C
pwr_cfg         MM      0x7E00F804
eint_mask       MM      0x7E00F808
normal_cfg      MM      0x7E00F810
stop_cfg        MM      0x7E00F814
sleep_cfg       MM      0x7E00F818
osc_freq        MM      0x7E00F820
osc_stable      MM      0x7E00F824
pwr_stable      MM      0x7E00F828
mtc_stable      MM      0x7E00F830
others          MM      0x7E00F900
rst_stat        MM      0x7E00F904
wakeup_stat     MM      0x7E00F908
blk_pwr_stat    MM      0x7E00F90C
inform0         MM      0x7E00FA00
inform1         MM      0x7E00FA04
inform2         MM      0x7E00FA08
inform3         MM      0x7E00FA0C
;
; SROM Cotroller
;
srom_bw         MM      0x70000000
srom_bc0        MM      0x70000004
srom_bc1        MM      0x70000008
srom_bc2        MM      0x7000000c
srom_bc3        MM      0x70000010
srom_bc4        MM      0x70000014
srom_bc5        MM      0x70000018
;
; 16-bit DRAM Controller
;
p0memstat       MM      0x7E000000
p0memccmd       MM      0x7E000004
p0directcmd     MM      0x7E000008
p0memcfg        MM      0x7E00000C
p0refresh       MM      0x7E000010
p0caslat        MM      0x7E000014
p0t_dqss        MM      0x7E000018
p0t_mrd         MM      0x7E00001C
p0t_ras         MM      0x7E000020
p0t_rc          MM      0x7E000024
p0t_rcd         MM      0x7E000028
p0t_rfc         MM      0x7E00002C
p0t_rp          MM      0x7E000030
p0t_rrd         MM      0x7E000034
p0t_wr          MM      0x7E000038
p0t_wtr         MM      0x7E00003C
p0t_xp          MM      0x7E000040
p0t_xsr         MM      0x7E000044
p0t_esr         MM      0x7E000048
p0memcfg2       MM      0x7E00004C
;
p0id0cfg        MM      0x7E000100
p0id1cfg        MM      0x7E000104
p0id2cfg        MM      0x7E000108
p0id3cfg        MM      0x7E00010C
p0id4cfg        MM      0x7E000110
p0id5cfg        MM      0x7E000114
p0id6cfg        MM      0x7E000118
p0id7cfg        MM      0x7E00011C
p0id8cfg        MM      0x7E000120
p0id9cfg        MM      0x7E000124
p0id10cfg       MM      0x7E000128
p0id11cfg       MM      0x7E00012C
p0id12cfg       MM      0x7E000130
p0id13cfg       MM      0x7E000134
p0id14cfg       MM      0x7E000138
p0id15cfg       MM      0x7E00013C
;
p0chip0cfg      MM      0x7E000200
p0chip1cfg      MM      0x7E000204
p0userstat      MM      0x7E000300
p0usercfg       MM      0x7E000304
;
; 32-bit DRAM Controller
;
p1memstat       MM      0x7E001000
p1memccmd       MM      0x7E001004
p1directcmd     MM      0x7E001008
p1memcfg        MM      0x7E00100C
p1refresh       MM      0x7E001010
p1caslat        MM      0x7E001014
p1t_dqss        MM      0x7E001018
p1t_mrd         MM      0x7E00101C
p1t_ras         MM      0x7E001020
p1t_rc          MM      0x7E001024
p1t_rcd         MM      0x7E001028
p1t_rfc         MM      0x7E00102C
p1t_rp          MM      0x7E001030
p1t_rrd         MM      0x7E001034
p1t_wr          MM      0x7E001038
p1t_wtr         MM      0x7E00103C
p1t_xp          MM      0x7E001040
p1t_xsr         MM      0x7E001044
p1t_esr         MM      0x7E001048
p1memcfg2       MM      0x7E00104C
;
p1id0cfg        MM      0x7E001100
p1id1cfg        MM      0x7E001104
p1id2cfg        MM      0x7E001108
p1id3cfg        MM      0x7E00110C
p1id4cfg        MM      0x7E001110
p1id5cfg        MM      0x7E001114
p1id6cfg        MM      0x7E001118
p1id7cfg        MM      0x7E00111C
p1id8cfg        MM      0x7E001120
p1id9cfg        MM      0x7E001124
p1id10cfg       MM      0x7E001128
p1id11cfg       MM      0x7E00112C
p1id12cfg       MM      0x7E001130
p1id13cfg       MM      0x7E001134
p1id14cfg       MM      0x7E001138
p1id15cfg       MM      0x7E00113C
;
p1chip0cfg      MM      0x7E001200
p1chip1cfg      MM      0x7E001204
p1userstat      MM      0x7E001300
p1usercfg       MM      0x7E001304
;
; Watchdog Timer
;
wtcon           MM      0x7E004000
wtdat           MM      0x7E004004
wtcnt           MM      0x7E004008
;

