;Register definition for iMX31
;=============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CPx	CPx register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CPx Registers Numbers for ARM11 cores:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
;
; CP15 Registers
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x2000          32      ;Cache type
tcmstatus       CP15    0x4000          32      ;TCM status
tlbtype         CP15    0x6000          32      ;TCM type
;
ctr             CP15    0x0001          32      ;Control
aux     	CP15    0x2001          32      ;Auxiliary Control
cpacc   	CP15    0x4001          32      ;Coprocessor Access
;
ttb0            CP15    0x0002          32      ;Translation Table Base 0
ttb1            CP15    0x2002          32      ;Translation Table Base 1
ttbc            CP15    0x4002          32      ;Translation Table Base Control
;
dac             CP15    0x0003          32      ;Domain Access Control
;
dfsr     	CP15    0x0005          32      ;Data Fault Status
ifsr     	CP15    0x2005          32      ;Instruction Fault Status
;
far     	CP15    0x0006          32      ;Fault Address
ifar     	CP15    0x2006          32      ;Instruction Fault Address
;
pid        	CP15    0x000d          32      ;Process ID
context        	CP15    0x200d          32      ;Context ID
;
;
; Cache debug access
;
cachedebug 	CP15    0x00ef          32      ;Cache debug control
dcachedata 	CP15    0x006f          32      ;Data Debug Cache
icachedata 	CP15    0x206f          32      ;Inst Debug Cache
dtagread   	CP15    0x026f          32      ;Read Data Tag RAM
itagread   	CP15    0x226f          32      ;Read Inst Tag RAM
idataread  	CP15    0x246f          32      ;Read Inst Data RAM
;
;
; MMU debug access
;
tlbdebug   	CP15    0x01ef          32      ;TLB debug control
dtlbread   	CP15    0x04af          32      ;Read Data Micro TLB entry
itlbread   	CP15    0x24af          32      ;Read Inst Micro TLB entry
mtlbread   	CP15    0x44af          32      ;Read Main       TLB entry
dtlbva     	CP15    0x05af          32      ;Data Micro TLB VA
itlbva     	CP15    0x25af          32      ;Inst Micro TLB VA
mtlbva     	CP15    0x45af          32      ;Main       TLB VA
dtlbpa     	CP15    0x06af          32      ;Data Micro TLB PA
itlbpa     	CP15    0x26af          32      ;Inst Micro TLB PA
mtlbpa     	CP15    0x46af          32      ;Main       TLB PA
dtlbattr   	CP15    0x07af          32      ;Data Micro TLB Attribute
itlbattr   	CP15    0x27af          32      ;Inst Micro TLB Attribute
mtlbattr   	CP15    0x47af          32      ;Main       TLB Attribute
;
;
; Debug Registers
;
didr       	CP14    0x0000          32      ;Debug ID
dscr       	CP14    0x0100          32      ;Debug Status and Control
dtr        	CP14    0x0500          32      ;Data Transfer
vcr        	CP14    0x0700          32      ;Vector Catch
;
bvr0       	CP14    0x8000          32      ;Breakpoint value
bvr1       	CP14    0x8100          32
bvr2       	CP14    0x8200          32
bvr3       	CP14    0x8300          32
bvr4       	CP14    0x8400          32
bvr5       	CP14    0x8500          32
;
wvr0       	CP14    0xc000          32      ;Watchpoint value
wvr1       	CP14    0xc100          32
;
;
; VFP11 Registers
;
fpsid      	CP10    0x00e0          32      ;FP System ID
fpscr      	CP10    0x00e1          32      ;FP Status and Control
fpexc      	CP10    0x00e8          32      ;FP Exception
fpinst     	CP10    0x00e9          32      ;FP Instruction
fpinst2    	CP10    0x00ea          32      ;FP Instruction 2
;
fps0         	CP10    0x0000          32      ;FP single-precision registers
fps1         	CP10    0x8000          32
fps2         	CP10    0x0001          32
fps3         	CP10    0x8001          32
fps4         	CP10    0x0002          32
fps5         	CP10    0x8002          32
fps6         	CP10    0x0003          32
fps7         	CP10    0x8003          32
fps8         	CP10    0x0004          32
fps9         	CP10    0x8004          32
fps10        	CP10    0x0005          32
fps11        	CP10    0x8005          32
fps12        	CP10    0x0006          32
fps13        	CP10    0x8006          32
fps14        	CP10    0x0007          32
fps15        	CP10    0x8007          32
fps16        	CP10    0x0008          32
fps17        	CP10    0x8008          32
fps18        	CP10    0x0009          32
fps19        	CP10    0x8009          32
fps20        	CP10    0x000a          32
fps21        	CP10    0x800a          32
fps22        	CP10    0x000b          32
fps23        	CP10    0x800b          32
fps24        	CP10    0x000c          32
fps25        	CP10    0x800c          32
fps26        	CP10    0x000d          32
fps27        	CP10    0x800d          32
fps28        	CP10    0x000e          32
fps29        	CP10    0x800e          32
fps30        	CP10    0x000f          32
fps31        	CP10    0x800f          32
;
;
; Clocks, Power Management and Reset (RSTC)
;
ccmr	        MM	0x53F80000
pdr0	        MM	0x53F80004
pdr1 	        MM	0x53F80008
rcsr 	        MM	0x53F8000C
mpctl	        MM	0x53F80010
upctl	        MM	0x53F80014
spctl	        MM	0x53F80018
cosr 	        MM	0x53F8001C
cgr0 	        MM	0x53F80020
cgr1 	        MM	0x53F80024
cgr2 	        MM	0x53F80028
wimr0	        MM	0x53F8002C
ldc  	        MM	0x53F80030
dcvr0	        MM	0x53F80034
dcvr1	        MM	0x53F80038
dcvr2	        MM	0x53F8003C
dcvr3	        MM	0x53F80040
ltr0 	        MM	0x53F80044
ltr1 	        MM	0x53F80048
ltr2 	        MM	0x53F8004C
ltr3 	        MM	0x53F80050
ltbr0	        MM	0x53F80054
ltbr1	        MM	0x53F80058
pmcr0	        MM	0x53F8005C
pmcr1	        MM	0x53F80060
pdr2 	        MM	0x53F80064
;
; Wireless External Interface Module (WEIM)
;
cscr0u	        MM	0xB8002000
cscr0l	        MM	0xB8002004
cscr0a	        MM	0xB8002008
cscr1u	        MM	0xB8002010
cscr1l	        MM	0xB8002014
cscr1a	        MM	0xB8002018
cscr2u	        MM	0xB8002020
cscr2l	        MM	0xB8002024
cscr2a	        MM	0xB8002028
cscr3u	        MM	0xB8002030
cscr3l	        MM	0xB8002034
cscr3a	        MM	0xB8002038
cscr4u	        MM	0xB8002040
cscr4l	        MM	0xB8002044
cscr4a	        MM	0xB8002048
cscr5u	        MM	0xB8002050
cscr5l	        MM	0xB8002054
cscr5a	        MM	0xB8002058
wcr   	        MM	0xB8002060