; ---------------------------------------
; bdiGDB configuration for STM32 with SWO
; ---------------------------------------
;
; Supported SWO baudrates above 115200:
;
; BDI2000: 122kb, 130kb, 139kb, 149kb, 160kb, 174kb, 189kb,
;          208kb, 232kb, 260kb, 298kb, 347kb, 417kb, 520kb
;
; BDI3000: 125kb, 133kb, 143kb, 154kb, 167kb, 182kb, 200kb,
;          222kb, 250kb, 285kb, 333kb, 400kb, 500kb
;

[INIT]
WGPR    13      0x20004ffc      ;set SP to top of internal SRAM
;
; prepare SWO ASCII output via Stimulus0
;
WM32    0xE00400F0  0x00000002  ;TPIU_PROTOCOL  : async mode NRZ
WM32    0xE0040010  26          ;TPIU_PRESCALER : select 298000 baud
WM32    0xE0040304  0x00000100  ;TPIU_FF_CONTROL: formatter bypass
;WM32    0xE0040304  0x00000102  ;TPIU_FF_CONTROL: enable formatter
WM32    0xE0042004  0x00000020  ;DBGMCU_CR      : enable trace IO
WM32    0xE0000FB0  0xC5ACCE55  ;ITM_LOCK_ACCESS: enable access
WM32    0xE0000E80  0x00000011  ;ITM_TRACE_CTRL : enable ITM and SWV
WM32    0xE0000E00  0x00000001  ;ITM_TRACE_ENA  : enable stimulus0
;


[TARGET]
CPUTYPE	    CORTEX-M3
CLOCK       2                   ;JTAG clock 8MHz
POWERUP     3000                ;start delay after power-up detected in ms
RESET	    HARD 100            ;assert reset for 100 ms
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
;
SWO         8023  298000        ;map ASCII SWO to odd  TCP port 8023
;SWO         8020  298000        ;map RAW   SWO to even TCP port 8020
;


[HOST]
IP          151.120.25.119
PROMPT	    SWO-M3>
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x20000000
DEBUGPORT   2001 RECONNECT


[FLASH]


[REGS]
FILE    $regCortex-M3.def