;Register definition for Luminary Micro LM3S ;=========================================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ; ;name type addr size ;------------------------------------------- ; sp_main GPR 17 32 ;Main Stackpointer sp_process GPR 18 32 ;Process Stackpointer ; ; Core debug registres dhcsr MM 0xE000EDF0 32 ;Debugging Halting Control and Status dcrsr MM 0xE000EDF4 32 ;Debug Core Register Selector dcrdr MM 0xE000EDF8 32 ;Debug Core Register Data demcr MM 0xE000EDFC 32 ;Debug Core Register Selector dfsr MM 0xE000ED30 32 ;Debug Fault Status ; ; System debug registres fp_ctrl MM 0xE0002000 32 ;Flash Patch Control fp_remap MM 0xE0002004 32 ;Flash Patch Remap fp_comp0 MM 0xE0002008 32 ;Flash Patch Comparator fp_comp1 MM 0xE000200C 32 ;Flash Patch Comparator fp_comp2 MM 0xE0002010 32 ;Flash Patch Comparator fp_comp3 MM 0xE0002014 32 ;Flash Patch Comparator fp_comp4 MM 0xE0002018 32 ;Flash Patch Comparator fp_comp5 MM 0xE000201C 32 ;Flash Patch Comparator fp_comp6 MM 0xE0002020 32 ;Flash Patch Comparator fp_comp7 MM 0xE0002024 32 ;Flash Patch Comparator ; dwt_ctrl MM 0xE0001000 32 ;DWT Control dwt_cyccnt MM 0xE0001004 32 ;DWT Current PC Sampler Count dwt_cpicnt MM 0xE0001008 32 ;DWT Current CPI Count dwt_exccnt MM 0xE000100C 32 ;DWT Current Interrupt Overhead Count dwt_sleepcnt MM 0xE0001010 32 ;DWT Current Sleep Count dwt_lsucnt MM 0xE0001014 32 ;DWT Current LSU Count dwt_foldcnt MM 0xE0001018 32 ;DWT Current Fold Count dwt_pcsr MM 0xE000101C 32 ;DWT PC Sample dwt_comp0 MM 0xE0001020 32 ;DWT Comparator dwt_mask0 MM 0xE0001024 32 ;DWT Mask dwt_function0 MM 0xE0001028 32 ;DWT Function dwt_comp1 MM 0xE0001030 32 ;DWT Comparator dwt_mask1 MM 0xE0001034 32 ;DWT Mask dwt_function1 MM 0xE0001038 32 ;DWT Function dwt_comp2 MM 0xE0001040 32 ;DWT Comparator dwt_mask2 MM 0xE0001044 32 ;DWT Mask dwt_function2 MM 0xE0001048 32 ;DWT Function dwt_comp3 MM 0xE0001050 32 ;DWT Comparator dwt_mask3 MM 0xE0001054 32 ;DWT Mask dwt_function3 MM 0xE0001058 32 ;DWT Function ; swo1 MM 0xE0000000 8 ;ITM 1 Byte Stimulus 0 swo2 MM 0xE0000000 16 ;ITM 2 Byte Stimulus 0 swo4 MM 0xE0000000 32 ;ITM 4 Byte Stimulus 0 itm_stimulus0 MM 0xE0000000 32 ;ITM Stimulus Ports 0-31 itm_stimulus1 MM 0xE0000004 32 itm_stimulus2 MM 0xE0000008 32 itm_stimulus3 MM 0xE000000C 32 itm_stimulus4 MM 0xE0000010 32 itm_stimulus5 MM 0xE0000014 32 itm_stimulus6 MM 0xE0000018 32 itm_stimulus7 MM 0xE000001C 32 itm_stimulus8 MM 0xE0000020 32 itm_stimulus9 MM 0xE0000024 32 itm_stimulus10 MM 0xE0000028 32 itm_stimulus11 MM 0xE000002C 32 itm_stimulus12 MM 0xE0000030 32 itm_stimulus13 MM 0xE0000034 32 itm_stimulus14 MM 0xE0000038 32 itm_stimulus15 MM 0xE000003C 32 itm_stimulus16 MM 0xE0000040 32 itm_stimulus17 MM 0xE0000044 32 itm_stimulus18 MM 0xE0000048 32 itm_stimulus19 MM 0xE000004C 32 itm_stimulus20 MM 0xE0000050 32 itm_stimulus21 MM 0xE0000054 32 itm_stimulus22 MM 0xE0000058 32 itm_stimulus23 MM 0xE000005C 32 itm_stimulus24 MM 0xE0000060 32 itm_stimulus25 MM 0xE0000064 32 itm_stimulus26 MM 0xE0000068 32 itm_stimulus27 MM 0xE000006C 32 itm_stimulus28 MM 0xE0000070 32 itm_stimulus29 MM 0xE0000074 32 itm_stimulus30 MM 0xE0000078 32 itm_stimulus31 MM 0xE000007C 32 itm_trace_ena MM 0xE0000E00 32 ;ITM Trace Enable itm_trace_priv MM 0xE0000E40 32 ;ITM Trace Privilege itm_trace_ctrl MM 0xE0000E80 32 ;ITM Trace Control itm_lock_access MM 0xE0000FB0 32 ;ITM Lock Access itm_lock_status MM 0xE0000FB4 32 ;ITM Lock Status ; tpiu_size_supp MM 0xE0040000 32 ;TPIU Supported Sync Port Sizes tpiu_size_curr MM 0xE0040004 32 ;TPIU Current Sync Port Size tpiu_prescaler MM 0xE0040010 32 ;TPIU Async Clock Prescaler tpiu_protocol MM 0xE00400F0 32 ;TPIU Selected Pin Protocol tpiu_ff_status MM 0xE0040300 32 ;TPIU Formatter and Flush Status tpiu_ff_control MM 0xE0040304 32 ;TPIU Formatter and Flush Control ; ; Flash registers flash_fma MM 0x400FD000 32 ;Flash Memory Address flash_fmd MM 0x400FD004 32 ;Flash Memory Data flash_fmc MM 0x400FD008 32 ;Flash Memory Control flash_fcris MM 0x400FD00C 32 ;Flash Controller Raw Interupt Status flash_fcim MM 0x400FD010 32 ;Flash Controller Interrupt Mask flash_fcmisc MM 0x400FD000 32 ;Flash Controller Masked Interupt Status and Clear ; flash_fmpre0 MM 0x400FE200 32 ;Flash Memory Protection Read Enable 0 flash_fmpre1 MM 0x400FE204 32 ;Flash Memory Protection Read Enable 1 flash_fmpre2 MM 0x400FE208 32 ;Flash Memory Protection Read Enable 2 flash_fmpre3 MM 0x400FE20C 32 ;Flash Memory Protection Read Enable 3 ; flash_fmppe0 MM 0x400FE400 32 ;Flash Memory Protection Program Enable 0 flash_fmppe1 MM 0x400FE400 32 ;Flash Memory Protection Program Enable 1 flash_fmppe2 MM 0x400FE400 32 ;Flash Memory Protection Program Enable 2 flash_fmppe3 MM 0x400FE400 32 ;Flash Memory Protection Program Enable 3 ; flash_usecrl MM 0x400FE140 32 ;Flash USec Reload flash_user_dbg MM 0x400FE1D0 32 ;Flash User Debug flash_user_reg0 MM 0x400FE1E0 32 ;Flash User Register 0 flash_user_reg1 MM 0x400FE1E4 32 ;Flash User Register 1 ; ; System Control registers sys_did0 MM 0x400FE000 32 ;Device ID 0 sys_did1 MM 0x400FE004 32 ;Device ID 1 sys_dc0 MM 0x400FE008 32 ;Device Capabilities 0 sys_dc1 MM 0x400FE010 32 ;Device Capabilities 1 sys_dc2 MM 0x400FE014 32 ;Device Capabilities 2 sys_dc3 MM 0x400FE018 32 ;Device Capabilities 3 sys_dc4 MM 0x400FE01C 32 ;Device Capabilities 4 sys_pborctl MM 0x400FE030 32 ;Brown-Out Reset Control sys_ldopctl MM 0x400FE034 32 ;LDO Power Control sys_srcr0 MM 0x400FE040 32 ;Software Reset Control 0 sys_srcr1 MM 0x400FE044 32 ;Software Reset Control 1 sys_srcr2 MM 0x400FE048 32 ;Software Reset Control 2 sys_ris MM 0x400FE050 32 ;Raw Interrupt Status sys_imc MM 0x400FE054 32 ;Interrupt Mask Control sys_misc MM 0x400FE058 32 ;Masked Interrupt Status and Clear sys_resc MM 0x400FE05C 32 ;Reset Cause sys_rcc MM 0x400FE060 32 ;Run-Mode Clock Configuration sys_pllcfg MM 0x400FE064 32 ;XTAL to PLL Translation sys_rcc2 MM 0x400FE070 32 ;Run-Mode Clock Configuration 2 sys_rcgc0 MM 0x400FE100 32 ;Run Mode Clock Gating Control 0 sys_rcgc1 MM 0x400FE104 32 ;Run Mode Clock Gating Control 1 sys_rcgc2 MM 0x400FE108 32 ;Run Mode Clock Gating Control 2 sys_scgc0 MM 0x400FE110 32 ;Sleep Mode Clock Gating Control 0 sys_scgc1 MM 0x400FE114 32 ;Sleep Mode Clock Gating Control 1 sys_scgc2 MM 0x400FE118 32 ;Sleep Mode Clock Gating Control 2 sys_dcgc0 MM 0x400FE120 32 ;Deep Sleep Mode Clock Gating Control 0 sys_dcgc1 MM 0x400FE124 32 ;Deep Sleep Mode Clock Gating Control 1 sys_dcgc2 MM 0x400FE128 32 ;Deep Sleep Mode Clock Gating Control 2 sys_dslpclkcfg MM 0x400FE144 32 ;Deep Sleep Clock Configuration ;