; ------------------------------------------
; bdiGDB configuration for Kinetis Cortex-M4
; ------------------------------------------
;

[INIT]
WGPR    13          0x20007ffc  ;set SP to top of internal SRAM
;
; for flash programming disable caches
WM32    0x4001F004  0x00080000  ;FMC_PFB0CR: invaliate and disable cache
;
; Disable Watchdog
WGPR    0           0x40052000  ;WDOG register base address
WGPR    1           0xC520      ;unlock code A
WGPR    2           0xD928      ;unlock code B
WGPR    3           0x01D2      ;New value for WDOG_STCTRLH
WM16    0x20000000  0x81c1      ;strh r1, [r0, #14]
WM16    0x20000002  0x81c2      ;strh r2, [r0, #14]
WM16    0x20000004  0x8003      ;strh r3, [r0, #0]
WM16    0x20000006  0xbe00      ;bkpt	0x0000
EXEC    0x20000000              ;execute disable code
;

[TARGET]
CPUTYPE	    CORTEX-M4
CLOCK       2                   ;JTAG clock 8MHz
POWERUP     3000                ;start delay after power-up detected in ms
RESET	    HARD 100            ;assert reset for 100 ms
;RESET	    SOFT                ;assert reset via Reset Control Register
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
;STARTUP     RUN                 ;let boot ROM setup the system
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
;


[HOST]
IP          151.120.25.119
PROMPT	    K40>
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x20000000


[FLASH]
CHIPTYPE    FTFL
WORKSPACE   0x20000000
FILE        E:/temp/dump16k.bin
FORMAT      BIN 0x00020000
ERASE       0x00020000 0x800 8  ;erase 8 x 2kB sectors


[REGS]
FILE    $regKinetis.def