; ----------------------------------
; bdiGDB configuration for Cortex-M0
; ----------------------------------
;

[INIT]
WGPR    13      0x10001ffc      ;set SP to top of internal SRAM


[TARGET]
CPUTYPE	    CORTEX-M0
CLOCK       2                   ;JTAG clock 8MHz
POWERUP     3000                ;start delay after power-up detected in ms
;RESET	    HARD 100            ;assert reset for 100 ms
RESET	    SOFT                ;assert reset via Reset Control Register
WAKEUP	    100                 ;wait after reset released
STARTUP     HALT                ;halt immediatelly at the reset vector
;STARTUP     RUN                 ;let boot ROM setup the system
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT                ;SOFT or HARD
MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
;


[HOST]
IP          151.120.25.119
PROMPT	    CTX-M0>
FILE        E:/temp/dump8k.bin
FORMAT      BIN 0x10000000
DEBUGPORT   2001 RECONNECT


[FLASH]


[REGS]
FILE    $regCortex-M0.def