;bdiGDB configuration file for P2041-RDB
;---------------------------------------
;
;
[INIT]
;
; setup device trigger, debug halt always all cores
; only writes to DCSR are processed for a running core
;WDCSR   0x22204         0x0000000f      ;CGCR0: Core Group 0 (0,1,2,3)
;WDCSR   0x2220c         0x0000000f      ;CGCR1: Core Group 1 (0,1,2,3)
;WDCSR   0x22214         0x0000000f      ;CGCR2: Core Group 2 (0,1,2,3)
;WDCSR   0x22700         0x00020001      ;CSTTACR0: trigger if a core from group 1 enter debug halt
;WDCSR   0x22610         0x00000022      ;CGACRD4 : if device event, halt cores in group 2
;
WREG    cgcr0           0x0000000f      ;CGCR0: Core Group 0 (0,1,2,3)
WREG    cgcr1           0x0000000f      ;CGCR1: Core Group 1 (0,1,2,3)
WREG    cgcr2           0x0000000f      ;CGCR2: Core Group 2 (0,1,2,3)
WREG    csttacr0        0x00020001      ;CSTTACR0: trigger if a core from group 1 enter debug halt
;
WREG    cgacrd4         0x00000022      ;CGACRD4 : if device event, halt cores in group 2
;
;WREG    epsmcr13        0x53000000      ;EPSMCR13[ISEL0] = 83 (RCPM Concerntrator 0 Event)
;WREG    epecr13         0x80000000      ;EPECR13[IC0]    = 2  (Input 0 is sufficient)
;WREG    cgacre13        0x00000022      ;CGACRE13: if EPU event, halt cores in group 2


[TARGET]
; common parameters
POWERUP     5000                ;start delay after power-up detected in ms
JTAGCLOCK   16000000            ;use 16 MHz JTAG clock
RESET       HARD  1000          ;assert reset for 1 seconds
WAKEUP      500                 ;give reset time to complete
;
;========================================================
; !!!! define the core ID (the #x) without any holes !!!!
; !!!! no need that core ID matches the core number  !!!!
; !!!! A valid example is: #1 CPUTYPE  P2041 2 0     !!!!
;========================================================
;
; CoreID#0 parameters (active core after reset)
#0 CPUTYPE      P2041 0 0       ;Core#0 / SOC#0
#0 EDBCR0       EDM DNH EFT     ;set run parameters
#0 STARTUP      STOP 3000       ;let core run
#0 BREAKMODE    HARD
#0 STEPMODE     HWBP
#0 MEMACCESS    CORE
#0 CGROUP       0x0f            ;GDB continue core group (resume)
;
; CoreID#1 parameters
#1 CPUTYPE      P2041 1 0       ;Core#1 / SOC#0
#1 EDBCR0       EDM DNH EFT     ;set run parameters
#1 STARTUP      RUN             ;let core run
#1 MEMACCESS    CORE
#1 CGROUP       0x02            ;GDB continue core group (prepare)
;
; CoreID#1 parameters
#2 CPUTYPE      P2041 2 0       ;Core#2 / SOC#0
#2 EDBCR0       EDM DNH EFT     ;set run parameters
#2 STARTUP      RUN             ;let core run
#2 MEMACCESS    CORE
#2 CGROUP       0x04            ;GDB continue core group (prepare)
;
; CoreID#1 parameters
#3 CPUTYPE      P2041 3 0       ;Core#3 / SOC#0
#3 EDBCR0       EDM DNH EFT     ;set run parameters
#3 STARTUP      RUN             ;let core run
#3 MEMACCESS    CORE
#3 CGROUP       0x08            ;GDB continue core group (prepare)
;


[HOST]
#0 PROMPT       P2041#0>
#1 PROMPT       P2041#1>
#2 PROMPT       P2041#2>
#3 PROMPT       P2041#3>


[FLASH]


[REGS]
FILE    $regP2041.def