;Register definition for T4240 ;============================= ; ; ;name type addr size ;------------------------------------------- ; sp GPR 1 64 ; ; extended 64-bit GPR's gpr0 GPR 0 64 gpr1 GPR 1 64 gpr2 GPR 2 64 gpr3 GPR 3 64 gpr4 GPR 4 64 gpr5 GPR 5 64 gpr6 GPR 6 64 gpr7 GPR 7 64 gpr8 GPR 8 64 gpr9 GPR 9 64 gpr10 GPR 10 64 gpr11 GPR 11 64 gpr12 GPR 12 64 gpr13 GPR 13 64 gpr14 GPR 14 64 gpr15 GPR 15 64 gpr16 GPR 16 64 gpr17 GPR 17 64 gpr18 GPR 18 64 gpr19 GPR 19 64 gpr20 GPR 20 64 gpr21 GPR 21 64 gpr22 GPR 22 64 gpr23 GPR 23 64 gpr24 GPR 24 64 gpr25 GPR 25 64 gpr26 GPR 26 64 gpr27 GPR 27 64 gpr28 GPR 28 64 gpr29 GPR 29 64 gpr30 GPR 30 64 gpr31 GPR 31 64 ; ; ; SPR's ; atbl SPR 526 64 atbu SPR 527 bucsr SPR 1013 cdcsr0 SPR 696 cir SPR 283 csrr0 SPR 58 64 csrr1 SPR 59 ctr SPR 9 64 dac1 SPR 316 64 dac2 SPR 317 64 dbcr0 SPR 308 dbcr1 SPR 309 dbcr2 SPR 310 dbcr4 SPR 563 dbcr5 SPR 564 dbrr0 SPR 700 dbsr SPR 304 dbsrwr SPR 306 ddam SPR 576 dear SPR 61 64 dec SPR 22 decar SPR 54 devent SPR 975 dsrr0 SPR 574 64 dsrr1 SPR 575 64 edbrac0 SPR 638 epcr SPR 307 eptcfg SPR 350 eplc SPR 947 epr SPR 702 epsc SPR 948 esr SPR 62 gdear SPR 381 64 gepr SPR 380 gesr SPR 383 givor13 SPR 444 givor14 SPR 445 givor2 SPR 440 givor3 SPR 441 givor35 SPR 464 givor4 SPR 442 givor8 SPR 443 givpr SPR 447 64 gpir SPR 382 gsprg0 SPR 368 64 gsprg1 SPR 369 64 gsprg2 SPR 370 64 gsprg3 SPR 371 64 gsrr0 SPR 378 64 gsrr1 SPR 379 hid0 SPR 1008 iac1 SPR 312 64 iac2 SPR 313 64 iac3 SPR 314 64 iac4 SPR 315 64 iac5 SPR 565 64 iac6 SPR 566 64 iac7 SPR 567 64 iac8 SPR 568 64 ivor0 SPR 400 ivor1 SPR 401 ivor10 SPR 410 ivor11 SPR 411 ivor12 SPR 412 ivor13 SPR 413 ivor14 SPR 414 ivor15 SPR 415 ivor2 SPR 402 ivor3 SPR 403 ivor32 SPR 528 ivor33 SPR 529 ivor35 SPR 531 ivor36 SPR 532 ivor37 SPR 533 ivor38 SPR 432 ivor39 SPR 433 ivor4 SPR 404 ivor40 SPR 434 ivor41 SPR 435 ivor42 SPR 436 ivor5 SPR 405 ivor6 SPR 406 ivor7 SPR 407 ivor8 SPR 408 ivor9 SPR 409 ivpr SPR 63 64 l1cfg0 SPR 515 l1cfg1 SPR 516 l1csr0 SPR 1010 l1csr1 SPR 1011 l1csr2 SPR 606 lpidr SPR 338 lr SPR 8 64 lratcfg SPR 342 lratps SPR 343 lper SPR 56 64 lperu SPR 57 mas0 SPR 624 mas0mas1 SPR 373 64 mas1 SPR 625 mas2 SPR 626 64 mas3 SPR 627 mas4 SPR 628 mas5 SPR 339 mas5mas6 SPR 348 64 mas6 SPR 630 mas7 SPR 944 mas7mas3 SPR 372 64 mas8 SPR 341 mas8mas1 SPR 349 64 mcar SPR 573 64 mcaru SPR 569 mcarua SPR 637 mcsr SPR 572 64 mcsrr0 SPR 570 64 mcsrr1 SPR 571 mmucfg SPR 1015 mmucsr0 SPR 1012 msrp SPR 311 npidr SPR 517 nspc SPR 984 nspd SPR 983 pid SPR 48 pir SPR 286 ppr32 SPR 898 pvr SPR 287 sprg0 SPR 272 64 sprg1 SPR 273 64 sprg2 SPR 274 64 sprg3_ro SPR 259 64 sprg3 SPR 275 64 sprg4_ro SPR 260 64 sprg4 SPR 276 64 sprg5_ro SPR 261 64 sprg5 SPR 277 64 sprg6_ro SPR 262 64 sprg6 SPR 278 64 sprg7_ro SPR 263 64 sprg7 SPR 279 64 sprg8 SPR 604 64 sprg9 SPR 605 64 srr0 SPR 26 64 srr1 SPR 27 svr SPR 1023 tbl_ro SPR 268 64 tbl SPR 284 tbu_ro SPR 269 tbu SPR 285 tcr SPR 340 tenc SPR 439 tens SPR 438 tensr SPR 437 tir SPR 446 tlb0cfg SPR 688 tlb0ps SPR 344 tlb1cfg SPR 689 tlb1ps SPR 345 tsr SPR 336 usprg0 SPR 256 xer SPR 1 64 ; ; ; Device Run Control (DCSR Space) dcdsr DCSR 0x2200C ;Device Core Debug Status cdsr0 DCSR 0x22100 ;Core Debug Status Register 0 cdsr1 DCSR 0x22104 ;Core Debug Status Register 1 cdsr2 DCSR 0x22108 ;Core Debug Status Register 2 cdsr3 DCSR 0x2210C ;Core Debug Status Register 3 cdsr4 DCSR 0x22110 ;Core Debug Status Register 4 cdsr5 DCSR 0x22114 ;Core Debug Status Register 5 cdsr6 DCSR 0x22118 ;Core Debug Status Register 6 cdsr7 DCSR 0x2211C ;Core Debug Status Register 7 ; ; ; L2 Cache Cluster 1 c1_l2csr0 CCSR 0xC20000 c1_l2csr1 CCSR 0xC20004 c1_l2cfg0 CCSR 0xC20008 c1_l2pir0 CCSR 0xC20200 c1_l2par0 CCSR 0xC20208 c1_l2pwr0 CCSR 0xC2020C c1_l2pir1 CCSR 0xC20210 c1_l2par1 CCSR 0xC20218 c1_l2pwr1 CCSR 0xC2021C c1_l2pir2 CCSR 0xC20220 c1_l2par2 CCSR 0xC20228 c1_l2pwr2 CCSR 0xC2022C c1_l2pir3 CCSR 0xC20230 c1_l2par3 CCSR 0xC20238 c1_l2pwr3 CCSR 0xC2023C c1_l2pir4 CCSR 0xC20240 c1_l2par4 CCSR 0xC20248 c1_l2pwr4 CCSR 0xC2024C c1_l2pir5 CCSR 0xC20250 c1_l2par5 CCSR 0xC20258 c1_l2pwr5 CCSR 0xC2025C c1_l2pir6 CCSR 0xC20260 c1_l2par6 CCSR 0xC20268 c1_l2pwr6 CCSR 0xC2026C c1_l2pir7 CCSR 0xC20270 c1_l2par7 CCSR 0xC20278 c1_l2pwr7 CCSR 0xC2027C c1_l2ipbrr1 CCSR 0xC20BF8 c1_l2ipbrr2 CCSR 0xC20BFC c1_l2errinjhi CCSR 0xC20E00 c1_l2errinjlo CCSR 0xC20E04 c1_l2errinjctl CCSR 0xC20E08 c1_l2captdatahi CCSR 0xC20E20 c1_l2captdatalo CCSR 0xC20E24 c1_l2captecc CCSR 0xC20E28 c1_l2errdet CCSR 0xC20E40 c1_l2errdis CCSR 0xC20E44 c1_l2errinten CCSR 0xC20E48 c1_l2errattr CCSR 0xC20E4C c1_l2erraddr CCSR 0xC20E50 c1_l2erreaddr CCSR 0xC20E54 c1_l2errctl CCSR 0xC20E58 c1_l2hdbcr0 CCSR 0xC20F00 c1_l2hdbcr1 CCSR 0xC20F04 c1_l2hdbcr2 CCSR 0xC20F08 ; ; Local Configuration Control ccsrbarh CCSR 0x000000 ccsrbarl CCSR 0x000004 ccsrar CCSR 0x000008 altcbarh CCSR 0x000010 altcbarl CCSR 0x000014 altcar CCSR 0x000018 bstrh CCSR 0x000020 bstrl CCSR 0x000024 bstrar CCSR 0x000028 ; ; Local Access Window lawbarh0 CCSR 0x000C00 lawbarl0 CCSR 0x000C04 lawar0 CCSR 0x000C08 lawbarh1 CCSR 0x000C10 lawbarl1 CCSR 0x000C14 lawar1 CCSR 0x000C18 lawbarh2 CCSR 0x000C20 lawbarl2 CCSR 0x000C24 lawar2 CCSR 0x000C28 lawbarh3 CCSR 0x000C30 lawbarl3 CCSR 0x000C34 lawar3 CCSR 0x000C38 lawbarh4 CCSR 0x000C40 lawbarl4 CCSR 0x000C44 lawar4 CCSR 0x000C48 lawbarh5 CCSR 0x000C50 lawbarl5 CCSR 0x000C54 lawar5 CCSR 0x000C58 lawbarh6 CCSR 0x000C60 lawbarl6 CCSR 0x000C64 lawar6 CCSR 0x000C68 lawbarh7 CCSR 0x000C70 lawbarl7 CCSR 0x000C74 lawar7 CCSR 0x000C78 lawbarh8 CCSR 0x000C80 lawbarl8 CCSR 0x000C84 lawar8 CCSR 0x000C88 lawbarh9 CCSR 0x000C90 lawbarl9 CCSR 0x000C94 lawar9 CCSR 0x000C98 lawbarh10 CCSR 0x000CA0 lawbarl10 CCSR 0x000CA4 lawar10 CCSR 0x000CA8 lawbarh11 CCSR 0x000CB0 lawbarl11 CCSR 0x000CB4 lawar11 CCSR 0x000CB8 lawbarh12 CCSR 0x000CC0 lawbarl12 CCSR 0x000CC4 lawar12 CCSR 0x000CC8 lawbarh13 CCSR 0x000CD0 lawbarl13 CCSR 0x000CD4 lawar13 CCSR 0x000CD8 lawbarh14 CCSR 0x000CE0 lawbarl14 CCSR 0x000CE4 lawar14 CCSR 0x000CE8 lawbarh15 CCSR 0x000CF0 lawbarl15 CCSR 0x000CF4 lawar15 CCSR 0x000CF8 ; lawbarh16 CCSR 0x000D00 lawbarl16 CCSR 0x000D04 lawar16 CCSR 0x000D08 lawbarh17 CCSR 0x000D10 lawbarl17 CCSR 0x000D14 lawar17 CCSR 0x000D18 lawbarh18 CCSR 0x000D20 lawbarl18 CCSR 0x000D24 lawar18 CCSR 0x000D28 lawbarh19 CCSR 0x000D30 lawbarl19 CCSR 0x000D34 lawar19 CCSR 0x000D38 lawbarh20 CCSR 0x000D40 lawbarl20 CCSR 0x000D44 lawar20 CCSR 0x000D48 lawbarh21 CCSR 0x000D50 lawbarl21 CCSR 0x000D54 lawar21 CCSR 0x000D58 lawbarh22 CCSR 0x000D60 lawbarl22 CCSR 0x000D64 lawar22 CCSR 0x000D68 lawbarh23 CCSR 0x000D70 lawbarl23 CCSR 0x000D74 lawar23 CCSR 0x000D78 lawbarh24 CCSR 0x000D80 lawbarl24 CCSR 0x000D84 lawar24 CCSR 0x000D88 lawbarh25 CCSR 0x000D90 lawbarl25 CCSR 0x000D94 lawar25 CCSR 0x000D98 lawbarh26 CCSR 0x000DA0 lawbarl26 CCSR 0x000DA4 lawar26 CCSR 0x000DA8 lawbarh27 CCSR 0x000DB0 lawbarl27 CCSR 0x000DB4 lawar27 CCSR 0x000DB8 lawbarh28 CCSR 0x000DC0 lawbarl28 CCSR 0x000DC4 lawar28 CCSR 0x000DC8 lawbarh29 CCSR 0x000DD0 lawbarl29 CCSR 0x000DD4 lawar29 CCSR 0x000DD8 lawbarh30 CCSR 0x000DE0 lawbarl30 CCSR 0x000DE4 lawar30 CCSR 0x000DE8 lawbarh31 CCSR 0x000DF0 lawbarl31 CCSR 0x000DF4 lawar31 CCSR 0x000DF8 ; ; Power Management tph10sr0 CCSR 0x0E200C tph10setr0 CCSR 0x0E201C tph10clrr CCSR 0x0E202C tph10psr0 CCSR 0x0E203C twaitsr0 CCSR 0x0E204C ; pcph15sr CCSR 0x0E20B0 pcph15setr CCSR 0x0E20B4 pcph15clrr CCSR 0x0E20B8 pcph15psr CCSR 0x0E20BC pcph20sr CCSR 0x0E20D0 pcph20setr CCSR 0x0E20D4 pcph20clrr CCSR 0x0E20D8 pcph20psr CCSR 0x0E20DC pcpw20sr CCSR 0x0E20E0 pcph30sr CCSR 0x0E20F0 pcph30setr CCSR 0x0E20F4 pcph30clrr CCSR 0x0E20F8 pcph30psr CCSR 0x0E20FC ippwrgatecr CCSR 0x0E2120 powmgtcsr CCSR 0x0E2130 ippdexpcr0 CCSR 0x0E2140 ; tpmimr0 CCSR 0x0E215C tpmcimr0 CCSR 0x0E216C tpmmcmr0 CCSR 0x0E217C tpmnmimr0 CCSR 0x0E218C tmcpmaskcr0 CCSR 0x0E219C ; pctbenr CCSR 0x0E21A0 pctbckselr CCSR 0x0E21A4 tbclkdivr CCSR 0x0E21A8 ttbhltcr0 CCSR 0x0E21BC ; clpcl10sr CCSR 0x0E21C0 clpcl10setr CCSR 0x0E21C4 clpcl10clrr CCSR 0x0E21C8 clpcl10psr CCSR 0x0E21CC cdpwroksetr CCSR 0x0E21D8 cdpwroksetr CCSR 0x0E21DC cdpwrensr CCSR 0x0E21E0 ; ; Local Bus Controller ifc_rev CCSR 0x124000 ifc_cspr0_ext CCSR 0x12400C ifc_cspr0 CCSR 0x124010 ; ; Device Configuration and Pin Control porsr1 CCSR 0x0E0000 porsr2 CCSR 0x0E0004 gpporcr1 CCSR 0x0E0020 gpporcr1 CCSR 0x0E0024 dcfg_fusesr CCSR 0x0E0028 devdisr1 CCSR 0x0E0070 devdisr2 CCSR 0x0E0074 devdisr3 CCSR 0x0E0078 devdisr4 CCSR 0x0E007C devdisr5 CCSR 0x0E0080 coredisr CCSR 0x0E0094 mmpvr CCSR 0x0E00A0 mmsvr CCSR 0x0E00A4 rstcr CCSR 0x0E00B0 rstrqpblsr CCSR 0x0E00B4 rstrqmr1 CCSR 0x0E00C0 rstrqsr1 CCSR 0x0E00C8 rstrqwdtmr CCSR 0x0E00D4 rstrqwdtsr CCSR 0x0E00DC brr CCSR 0x0E00E4 ; rcwsr1 CCSR 0x0E0100 rcwsr2 CCSR 0x0E0104 rcwsr3 CCSR 0x0E0108 rcwsr4 CCSR 0x0E010C rcwsr5 CCSR 0x0E0110 rcwsr6 CCSR 0x0E0114 rcwsr7 CCSR 0x0E0118 rcwsr8 CCSR 0x0E011C rcwsr9 CCSR 0x0E0120 rcwsr10 CCSR 0x0E0124 rcwsr11 CCSR 0x0E0128 rcwsr12 CCSR 0x0E012C rcwsr13 CCSR 0x0E0130 rcwsr14 CCSR 0x0E0134 rcwsr15 CCSR 0x0E0138 rcwsr16 CCSR 0x0E013C ; crstsr0 CCSR 0x0E0400 crstsr1 CCSR 0x0E0404 crstsr2 CCSR 0x0E0408 crstsr3 CCSR 0x0E040C crstsr4 CCSR 0x0E0410 crstsr5 CCSR 0x0E0414 crstsr6 CCSR 0x0E0418 crstsr7 CCSR 0x0E041C crstsr8 CCSR 0x0E0420 crstsr9 CCSR 0x0E0424 crstsr10 CCSR 0x0E0428 crstsr11 CCSR 0x0E042C ; ; CoreNet Platform Cache (CPC) ; cpc1_csr0 CCSR 0x010000 cpc1_cfg0 CCSR 0x010008 cpc1_ewcr0 CCSR 0x010010 cpc1_ewbar0 CCSR 0x010014 cpc1_ewcr1 CCSR 0x010020 cpc1_ewbar1 CCSR 0x010024 cpc1_srcr1 CCSR 0x010100 cpc1_srcr0 CCSR 0x010104 cpc1_pir0 CCSR 0x010200 cpc1_par0 CCSR 0x010208 cpc1_pwr0 CCSR 0x01020C cpc1_pir1 CCSR 0x010210 cpc1_par1 CCSR 0x010218 cpc1_pwr1 CCSR 0x01021C cpc1_pir2 CCSR 0x010220 cpc1_par2 CCSR 0x010228 cpc1_pwr2 CCSR 0x01022C cpc1_pir3 CCSR 0x010230 cpc1_par3 CCSR 0x010238 cpc1_pwr3 CCSR 0x01023C cpc1_pir4 CCSR 0x010240 cpc1_par4 CCSR 0x010248 cpc1_pwr4 CCSR 0x01024C cpc1_pir5 CCSR 0x010250 cpc1_par5 CCSR 0x010258 cpc1_pwr5 CCSR 0x01026C cpc1_pir6 CCSR 0x010260 cpc1_par6 CCSR 0x010268 cpc1_pwr6 CCSR 0x01026C cpc1_pir7 CCSR 0x010270 cpc1_par7 CCSR 0x010278 cpc1_pwr7 CCSR 0x01027C cpc1_pir8 CCSR 0x010280 cpc1_par8 CCSR 0x010288 cpc1_pwr8 CCSR 0x01028C cpc1_pir9 CCSR 0x010290 cpc1_par9 CCSR 0x010298 cpc1_pwr9 CCSR 0x01029C cpc1_pir10 CCSR 0x0102A0 cpc1_par10 CCSR 0x0102A8 cpc1_pwr10 CCSR 0x0102AC cpc1_pir11 CCSR 0x0102B0 cpc1_par11 CCSR 0x0102B8 cpc1_pwr11 CCSR 0x0102BC cpc1_pir12 CCSR 0x0102C0 cpc1_par12 CCSR 0x0102C8 cpc1_pwr12 CCSR 0x0102CC cpc1_pir13 CCSR 0x0102D0 cpc1_par13 CCSR 0x0102D8 cpc1_pwr13 CCSR 0x0102DC cpc1_pir14 CCSR 0x0102E0 cpc1_par14 CCSR 0x0102E8 cpc1_pwr14 CCSR 0x0102EC cpc1_pir15 CCSR 0x0102F0 cpc1_par15 CCSR 0x0102F8 cpc1_pwr15 CCSR 0x0102FC cpc1_errinjhi CCSR 0x010E00 cpc1_errinjlo CCSR 0x010E04 cpc1_errinjctl CCSR 0x010E08 cpc1_captdatahi CCSR 0x010E20 cpc1_captdatalo CCSR 0x010E24 cpc1_captecc CCSR 0x010E28 cpc1_errdet CCSR 0x010E40 cpc1_errdis CCSR 0x010E44 cpc1_errinten CCSR 0x010E48 cpc1_errattr CCSR 0x010E4C cpc1_erreaddr CCSR 0x010E50 cpc1_erraddr CCSR 0x010E54 cpc1_errctl CCSR 0x010E58 cpc1_hdbcr0 CCSR 0x010F00 ; ; DDR Memory Controller ; ddr1_cs0_bnds CCSR 0x008000 ddr1_cs1_bnds CCSR 0x008008 ddr1_cs2_bnds CCSR 0x008010 ddr1_cs3_bnds CCSR 0x008018 ddr1_cs0_cfg CCSR 0x008080 ddr1_cs1_cfg CCSR 0x008084 ddr1_cs2_cfg CCSR 0x008088 ddr1_cs3_cfg CCSR 0x00808C ddr1_cs0_cfg_2 CCSR 0x0080C0 ddr1_cs1_cfg_2 CCSR 0x0080C4 ddr1_cs2_cfg_2 CCSR 0x0080C8 ddr1_cs3_cfg_2 CCSR 0x0080CC ddr1_tim_cfg_3 CCSR 0x008100 ddr1_tim_cfg_0 CCSR 0x008104 ddr1_tim_cfg_1 CCSR 0x008108 ddr1_tim_cfg_2 CCSR 0x00810C ddr1_ram_cfg CCSR 0x008110 ddr1_ram_cfg_2 CCSR 0x008114 ddr1_ram_mode CCSR 0x008118 ddr1_ram_mode_2 CCSR 0x00811C ddr1_md_cntl CCSR 0x008120 ddr1_interval CCSR 0x008124 ddr1_data_init CCSR 0x008128 ddr1_clk_ctl CCSR 0x008130 ddr1_init_addr CCSR 0x008148 ddr1_init_exta CCSR 0x00814C ddr1_tim_cfg_4 CCSR 0x008160 ddr1_tim_cfg_5 CCSR 0x008164 ddr1_zq_ctl CCSR 0x008170 ddr1_wrlvl_ctl CCSR 0x008174 ddr1_sr_cntr CCSR 0x00817C ddr1_sdram_rcw1 CCSR 0x008180 ddr1_sdram_rcw2 CCSR 0x008184 ddr1_wrlvl_ctl2 CCSR 0x008190 ddr1_wrlvl_ctl3 CCSR 0x008194 ddr1_ram_mode_3 CCSR 0x008200 ddr1_ram_mode_4 CCSR 0x008204 ddr1_ram_mode_5 CCSR 0x008208 ddr1_ram_mode_6 CCSR 0x00820C ddr1_ram_mode_7 CCSR 0x008210 ddr1_ram_mode_8 CCSR 0x008214 ddr1_dsr_1 CCSR 0x008B20 ddr1_dsr_2 CCSR 0x008B24 ddr1_cdr_1 CCSR 0x008B28 ddr1_cdr_2 CCSR 0x008B2C ddr1_ip_rev1 CCSR 0x008BF8 ddr1_ip_rev2 CCSR 0x008BFC ddr1_mtcr CCSR 0x008D00 ddr1_mtp1 CCSR 0x008D20 ddr1_mtp2 CCSR 0x008D24 ddr1_mtp3 CCSR 0x008D28 ddr1_mtp4 CCSR 0x008D2C ddr1_mtp5 CCSR 0x008D30 ddr1_mtp6 CCSR 0x008D34 ddr1_mtp7 CCSR 0x008D38 ddr1_mtp8 CCSR 0x008D3C ddr1_mtp9 CCSR 0x008D40 ddr1_mtp10 CCSR 0x008D44 ddr1_dat_err_hi CCSR 0x008E00 ddr1_dat_err_lo CCSR 0x008E04 ddr1_ecc_erri CCSR 0x008E08 ddr1_cap_datahi CCSR 0x008E20 ddr1_cap_datalo CCSR 0x008E24 ddr1_cap_ecc CCSR 0x008E28 ddr1_err_detect CCSR 0x008E40 ddr1_err_dis CCSR 0x008E44 ddr1_err_int_en CCSR 0x008E48 ddr1_cap_attr CCSR 0x008E4C ddr1_cap_addr CCSR 0x008E50 ddr1_cap_exta CCSR 0x008E54 ddr1_err_sbe CCSR 0x008E58 ;