;bdiGDB configuration file for P5040-DS
;--------------------------------------
;
;
[INIT]
;
; Setup TLB1
;          MAS1       MAS2       MAS0/MAS7     MAS3
WTLB    0x80000700_0xfe00000a   0x10010000_0xfe00003f   ;1/1: fe000000->0_fe000000  16MB -I-G- RWXRWX
WTLB    0x80000900_0xe000000a   0x10020000_0xe000003f   ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX
WTLB    0x80000a00_0x00000000   0x10030000_0x0000003f   ;1/3: 00000000->0_00000000   1GB ----- RWXRWX
WTLB    0x80000a00_0x40000000   0x10040000_0x4000003f   ;1/4: 40000000->0_40000000   1GB ----- RWXRWX
WTLB    0x80000500_0x80000000   0x10050000_0x8000003f   ;1/5: 80000000->0_80000000   1MB ----- RWXRWX
;
;
; Initialize LAWBAR's
WM32    0xfe000c00      0x00000000      ;LAWBAR0 : Flash @0_e0000000
WM32    0xfe000c04      0xe0000000
WM32    0xfe000c08      0x81f0001b      ;LAWAR0  : eLBC 256MB
;
WM32    0xfe000c10      0x00000000      ;LAWBAR1 : CPC1/SRAM @0_80000000
WM32    0xfe000c14      0x80000000
WM32    0xfe000c18      0x81000013      ;LAWAR1  : DDR1/CPC1 1MB
;
WM32    0xfe000df0      0x00000000      ;LAWBAR31: SDRAM @0_00000000
WM32    0xfe000df4      0x00000000
WM32    0xfe000df8      0x8100001e      ;LAWAR31 : DDR1/CPC1 2GB
;
; Use L3 cache (CPC1) as SRAM at 0x80000000
WM32    0xfe010100      0x00000000      ;CPC1_SRCR1 : high address
WM32    0xfe010104      0x8000000b      ;CPC1_SRCR0 : all 32 ways as SRAM
WM32    0xfe010000      0x80000000      ;CPC1_CSR0  : CPC enable
WM32    0xfe010f00      0x08000000      ;CPC1_HDBCR0: Speculation disable
;
; Local Bus Controller
WM32    0xfe124004      0xf8000ff7      ;OR0:
WM32    0xfe124000      0xe8001001      ;BR0:
;


[TARGET]
; common parameters
POWERUP     5000                ;start delay after power-up detected in ms
JTAGCLOCK   2                   ;use 4 MHz JTAG clock
RESET       HARD  500           ;assert reset for 0.5 seconds
WAKEUP      200                 ;give reset time to complete
;
; CoreID#0 parameters (active vCPU after reset)
CPUTYPE      P5040 0 0          ;Core#0 / SOC#0
EDBCR0       EDM DNH EFT        ;set run parameters
STARTUP      HALT               ;halt at the reset vector (this halts all cores !!!)
BREAKMODE    HARD               ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE     HWBP               ;ICMP or HWBP, HWBP uses a hardware breakpoint
;
; RCW Override for SOC#0 assigned to CoreID#0
; don't override PLL configuration in RCW[0]-RCW[3]
;#0 RCWSRC       0x18            ;Hard-Coded RCW 1_1000
;#0 RCWOVR  0    0x10600000      ;  0: don't override !!!
;#0 RCWOVR  1    0x00000000      ; 32: don't override !!!
;#0 RCWOVR  2    0x2c2c1800      ; 64: don't override !!!
;#0 RCWOVR  3    0x00440000      ; 96: don't override !!!
;#0 RCWOVR  4    0x089c4400      ;128:
;#0 RCWOVR  5    0x00283000      ;160:
;#0 RCWOVR  6    0xfe800000      ;192:
;#0 RCWOVR  7    0x61000000      ;224:
;#0 RCWOVR  8    0x00000000      ;256:
;#0 RCWOVR  9    0x00000000      ;288:
;#0 RCWOVR  10   0x00000000      ;320:
;#0 RCWOVR  11   0x10070001      ;352:
;#0 RCWOVR  12   0xa8000000      ;384:
;#0 RCWOVR  13   0x00000000      ;416:
;#0 RCWOVR  14   0x00000000      ;448:
;#0 RCWOVR  15   0x00000000      ;480:
;

[HOST]
IP              151.120.25.119
FILE            E:\temp\dump1024k.bin
FORMAT          BIN 0x80000000
PROMPT          PROG5040>

[FLASH]
;flash is S29GL01GP
WORKSPACE   0x80001000          ;workspace in CPC1/SRAM
CHIPTYPE    MIRRORX16           ;Flash type is S29GL01GP
CHIPSIZE    0x08000000          ;The size of one flash chip in bytes
BUSWIDTH    16                  ;The width of the flash memory bus in bits
;FILE        E:\temp\dump256k.bin
;FORMAT      BIN 0xed800000
;ERASE       0xed800000 0x20000 4
;
FILE        E:\temp\bootloop.bin
FORMAT      BIN 0xefffff00
ERASE       0xeffe0000
;


[REGS]
FILE        $regP5040.def