;bdiGDB configuration file for T4240-QDS
;---------------------------------------
;
[INIT]
;
; Setup TLB1
;          MAS1       MAS2       MAS0/MAS7     MAS3
WTLB    0x80000700_0xff00000a   0x10000000_0xff00003f   ;1/0: ff000000->0_ff000000  16MB -I-G- RWXRWX
WTLB    0x80000700_0xfe00000a   0x10010000_0xfe00003f   ;1/1: fe000000->0_fe000000  16MB -I-G- RWXRWX
WTLB    0x80000900_0xe000000a   0x10020000_0xe000003f   ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX
WTLB    0x80000a00_0x00000000   0x10030000_0x0000003f   ;1/3: 00000000->0_00000000   1GB ----- RWXRWX
WTLB    0x80000a00_0x40000000   0x10040000_0x4000003f   ;1/4: 40000000->0_40000000   1GB ----- RWXRWX
WTLB    0x80000500_0x80000000   0x10050000_0x8000003f   ;1/5: 80000000->0_80000000   1MB ----- RWXRWX
;
; Initialize LAWBAR's
WM32    0xfe000c00      0x00000000      ;LAWBAR0 : Flash @0_e0000000
WM32    0xfe000c04      0xe0000000
WM32    0xfe000c08      0x81f0001b      ;LAWAR0  : eLBC 256MB
;
WM32    0xfe000c10      0x00000000      ;LAWBAR1 : CPC1/SRAM @0_80000000
WM32    0xfe000c14      0x80000000
WM32    0xfe000c18      0x81000013      ;LAWAR1  : DDR1/CPC1 1MB
;
WM32    0xfe000df0      0x00000000      ;LAWBAR31: SDRAM @0_00000000
WM32    0xfe000df4      0x00000000
WM32    0xfe000df8      0x8100001e      ;LAWAR31 : DDR1/CPC1 2GB
;
; Integrated Flash Controller (IFC)
WREG    ifc_cspr0_ext   0x00000000      ;Map 8MByte of NOR Flash to 0xff800000
WREG    ifc_cspr0       0xff800101
WREG    ifc_amask0      0xff800000
;
;WREG    ifc_cspr0_ext   0x00000000      ;Map 128 MByte of NOR Flash to 0xe8000000
;WREG    ifc_cspr0       0xe8000101
;WREG    ifc_amask0      0xf8000000
;
; Use L3 cache (CPC1) as SRAM at 0x80000000
WM32    0xfe010100      0x00000000      ;CPC1_SRCR1 : high address
WM32    0xfe010104      0x8000000b      ;CPC1_SRCR0 : all 32 ways as SRAM
WM32    0xfe010000      0x80000000      ;CPC1_CSR0  : CPC enable
WM32    0xfe010f00      0x08000000      ;CPC1_HDBCR0: Speculation disable
;
; write DNH instruction to default vector
WM32	0x80000000	    0x4c00018c	    ;catch default vector
;
; write a loop to CPC1/SRAM
WM32    0x80000100      0x386003e8      ;li     r3,1000
WM32    0x80000104      0x38800000      ;li     r4,0
WM32    0x80000108      0x38a00000      ;li     r5,0
WM32    0x8000010c      0x38a50008      ;addi   r5,r5,8
WM32    0x80000110      0x38840008      ;addi   r4,r4,8
WM32    0x80000114      0x3463ffff      ;addic. r3,r3,-1
WM32    0x80000118      0x4082fff4      ;bne    bc <TestLoop>
WM32    0x8000011c      0x4bffffe4      ;b      b0 <Test>
WM32    0x80000120      0x60000000      ;nop
WM32    0x80000124      0x60000000      ;nop
;
; set PC to start of loop
#0 WREG pc              0x80000100
;
; set default vector
#0 WREG ivpr            0x80000000
;


[TARGET]
; common parameters
POWERUP     5000                ;start delay after power-up detected in ms
JTAGCLOCK   16000000            ;16 MHz JTAG clock
RESET       HARD  1000          ;assert reset for 1 seconds
WAKEUP      500                 ;give reset time to complete
;
;===========================================================
; !!!! define the thread ID (the #x) without any holes  !!!!
; !!!! no need that thread ID matches the thread number !!!!
; !!!! A valid example is: #1 CPUTYPE  T4240 2 0        !!!!
;===========================================================
;
; ThreadID#0 parameters (active thread after reset)
#0 CPUTYPE      T4240 0 0       ;Thread#0 / SOC#0
#0 EDBCR0       EDM DNH CTH     ;set run parameters (don't set EFT)
#0 STARTUP      HALT            ;halt at the reset vector (this halts all threads !!!)
#0 BREAKMODE    HARD            ;SOFT or HARD, HARD uses PPC hardware breakpoint
#0 STEPMODE     HWBP            ;ICMP or HWBP, HWBP uses a hardware breakpoint
;
;#0 RCWOVR  0    0x14060019      ;0:


[HOST]
FILE            E:\temp\dump256k.bin
FORMAT          BIN 0x80000000
;
#0 PROMPT       T4240#0>


[FLASH]
;flash is S29GL01GS
WORKSPACE   0x80001000          ;workspace in CPC1/SRAM
CHIPTYPE    MIRRORX16           ;Flash type is S29GL01GS
CHIPSIZE    0x00800000          ;visible size of one flash chip in bytes
BUSWIDTH    16                  ;The width of the flash memory bus in bits
FILE        E:\temp\dump256k.bin
FORMAT      BIN 0xffe00000
ERASE       0xffe00000 0x20000 4


[REGS]
FILE        $regT4240.def