;bdiGDB configuration file for P3041-DS ;-------------------------------------- ; ; mmh 0xe8000aaa 0x00aa ;PPB entry ; mmh 0xe8000554 0x0055 ; mmh 0xe8000aaa 0x00c0 ; ; mmh 0xe8000000 0x0090 ;PPB exit ; mmh 0xe8000000 0x0000 ; ; mmh 0xe8000000 0x00a0 ;PPB program ; mmh 0xe8000000 0x0000 ; ; mmh 0xe8000000 0x0080 ;PPB erase ; mmh 0xe8000000 0x0030 ; mdh 0xe8000000 ; ; [INIT] ; ; Setup TLB1 ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX WTLB 0x80000500_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 1MB ----- RWXRWX ; ;========================================================================================= ; Setup TLB0 (for test purpose only) ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000100_0xc0000000 0x00000000_0x0000003f ;WAY0: c0000000->0_00000000 4KB ----- RWXRWX WTLB 0x80000100_0xc0001000 0x00000000_0x0000103f ;WAY0: c0001000->0_00001000 4KB ----- RWXRWX WTLB 0x80000100_0xc0002000 0x00000000_0x0000203f ;WAY0: c0002000->0_00002000 4KB ----- RWXRWX WTLB 0x80000100_0xc0003000 0x00000000_0x0000303f ;WAY0: c0003000->0_00003000 4KB ----- RWXRWX ;========================================================================================= ; ; Initialize LAWBAR's WM32 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 WM32 0xfe000c04 0xe0000000 WM32 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB ; WM32 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 WM32 0xfe000c14 0x80000000 WM32 0xfe000c18 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB ; WM32 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 WM32 0xfe000df4 0x00000000 WM32 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WM32 0xfe010100 0x00000000 ;CPC1_SRCR1 : high address WM32 0xfe010104 0x8000000b ;CPC1_SRCR0 : all 32 ways as SRAM WM32 0xfe010000 0x80000000 ;CPC1_CSR0 : CPC enable WM32 0xfe010f00 0x08000000 ;CPC1_HDBCR0: Speculation disable ; ; Local Bus Controller WM32 0xfe124004 0xf8000ff7 ;OR0: WM32 0xfe124000 0xe8001001 ;BR0: WM32 0xfe12400c 0xf8000ff7 ;OR1: WM32 0xfe124008 0xe0001001 ;BR1: WM32 0xfe12401c 0xffff8ff7 ;OR3: ngPIXIS (FPGA) WM32 0xfe124018 0xffdf0801 ;BR3: ; ;TSZ8 0x00000000 0xffffffff ; [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 2 ;use 4 MHz JTAG clock RESET HARD 1000 ;assert reset for 0.5 seconds WAKEUP 500 ;give reset time to complete ;SDCRESP 0x01aa00bbcafeca77 ;SDC challenge/response ;SDCRESP 0xffffffffffffffff ;Enter SDC challenge mode ;MEMACCESS SAP 10 ;memory access via SAP (10us access delay) ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE P4080 5 0 !!!! ;======================================================== ; ; CoreID#0 parameters (active vCPU after reset) #0 CPUTYPE P3041 0 0 ;Core#0 / SOC#0 #0 EDBCR0 EDM DNH EFT ;set run parameters #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint ; ;SCANPRED 1 1 ;SCANSUCC 1 1 ; ; RCW Override for SOC#0 assigned to CoreID#0 ; don't override PLL configuration in RCW[0]-RCW[3] ;#0 RCWSRC 0x18 ;Hard-Coded RCW 1_1000 ;#0 RCWOVR 0 0x4c140000 ; 0: don't override !!! ;#0 RCWOVR 1 0x00000000 ; 32: don't override !!! ;#0 RCWOVR 2 0x12121414 ; 64: don't override !!! ;#0 RCWOVR 3 0x00008888 ; 96: don't override !!! ;#0 RCWOVR 4 0x00000000 ;128: ;#0 RCWOVR 5 0x00000000 ;160: ;#0 RCWOVR 6 0xfe800000 ;192: ;#0 RCWOVR 7 0x01000000 ;224: ;#0 RCWOVR 8 0x00000000 ;256: ;#0 RCWOVR 9 0x00000000 ;288: ;#0 RCWOVR 10 0x00000000 ;320: ;#0 RCWOVR 11 0xc0030000 ;352: ;#0 RCWOVR 12 0x00000000 ;384: ;#0 RCWOVR 13 0x00000000 ;416: ;#0 RCWOVR 14 0x00000000 ;448: ;#0 RCWOVR 15 0x00000000 ;480: ; ;#0 RCWOVR 0 0x4c100000 ; 0: don't override !!! ;#0 RCWOVR 1 0x00000000 ; 32: don't override !!! ;#0 RCWOVR 2 0x18140000 ; 64: don't override !!! ;#0 RCWOVR 3 0x00000000 ; 96: don't override !!! ;#0 RCWOVR 4 0xd8602a00 ;128: ;#0 RCWOVR 5 0x00002000 ;160: ;#0 RCWOVR 6 0xfe800000 ;192: ;#0 RCWOVR 7 0x40000000 ;224: ;#0 RCWOVR 8 0x00000000 ;256: ;#0 RCWOVR 9 0x00000000 ;288: ;#0 RCWOVR 10 0x00000000 ;320: ;#0 RCWOVR 11 0xd0c30001 ;352: ;#0 RCWOVR 12 0xa8000000 ;384: ;#0 RCWOVR 13 0x00000000 ;416: ;#0 RCWOVR 14 0x00000000 ;448: ;#0 RCWOVR 15 0x00000000 ;480: ; ; ; ; CoreID#1 parameters #1 CPUTYPE P3041 1 0 ;Core#1 / SOC#0 #1 EDBCR0 EDM DNH EFT ;set run parameters #1 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #2 CPUTYPE P3041 2 0 ;Core#2 / SOC#0 #2 EDBCR0 EDM DNH EFT ;set run parameters #2 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #3 CPUTYPE P3041 3 0 ;Core#3 / SOC#0 #3 EDBCR0 EDM DNH EFT ;set run parameters #3 STARTUP HALT ;halt at the reset vector ; [HOST] IP 151.120.25.119 FILE E:\temp\dump256k.bin FORMAT BIN 0x80000000 ; #0 PROMPT P3041#0> #1 PROMPT P3041#1> #2 PROMPT P3041#2> #3 PROMPT P3041#3> ; [FLASH] ;flash is S29GL01GP WORKSPACE 0x80001000 ;workspace in CPC1/SRAM CHIPTYPE MIRRORX16 ;Flash type is S29GL01GP CHIPSIZE 0x08000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits FILE E:\temp\dump256k.bin FORMAT BIN 0xed800000 ERASE 0xed800000 0x20000 4 [REGS] FILE $regP3041.def DMM1 0xffdf0000 ;ngPIXIS (FPGA)