;bdiGDB configuration file for P2041-RDB
;---------------------------------------
;
;
[INIT]
;
; Setup TLB1
;          MAS1       MAS2       MAS0/MAS7     MAS3
WREG    hid0                    0x00000080              ;enable MAS7 update
WTLB    0x80000700_0xfe00000a   0x10010000_0xfe00003f   ;1/1: fe000000->0_fe000000  16MB -I-G- RWXRWX
WTLB    0x80000900_0xe000000a   0x1002000f_0xe000003f   ;1/2: e0000000->f_e0000000 256MB -I-G- RWXRWX


[TARGET]
; common parameters
POWERUP     5000                ;start delay after power-up detected in ms
;JTAGCLOCK   1                   ;BDI3000: use 16 MHz JTAG clock
JTAGCLOCK   0                   ;BDI2000: use 16 MHz JTAG clock
RESET       HARD  1000          ;assert reset for 0.5 seconds
WAKEUP      500                 ;give reset time to complete
;
;========================================================
; !!!! define the core ID (the #x) without any holes !!!!
; !!!! no need that core ID matches the core number  !!!!
; !!!! A valid example is: #1 CPUTYPE  P2041 2 0     !!!!
;========================================================
;
; CoreID#0 parameters (active vCPU after reset)
#0 CPUTYPE      P2041 0 0       ;Core#0 / SOC#0
#0 STARTUP      HALT            ;halt at the reset vector (this halts all cores !!!)
#0 BREAKMODE    HARD            ;SOFT or HARD, HARD uses PPC hardware breakpoint
#0 STEPMODE     HWBP            ;ICMP or HWBP, HWBP uses a hardware breakpoint
;
; CoreID#1 parameters
#1 CPUTYPE      P2041 1 0       ;Core#1 / SOC#0
#1 STARTUP      HALT            ;halt at the reset vector
;
; CoreID#1 parameters
#2 CPUTYPE      P2041 2 0       ;Core#2 / SOC#0
#2 STARTUP      HALT            ;halt at the reset vector
;
; CoreID#1 parameters
#3 CPUTYPE      P2041 3 0       ;Core#3 / SOC#0
#3 STARTUP      HALT            ;halt at the reset vector
;


[HOST]
#0 PROMPT       P2041#0>
#1 PROMPT       P2041#1>
#2 PROMPT       P2041#2>
#3 PROMPT       P2041#3>


[FLASH]


[REGS]
FILE        $regP2041.def