;Register definition for PPC460EX
;================================
;
; name: user defined name of the register
; type: the type of the register
;   GPR general purpose register
;   SPR special purpose register
;   MM  memory mapped register
;   DMMx    direct memory mapped register with offset
;       x = 1..4
;       the base is defined in the configuration file
;       e.g. DMM1 0x02200000
;   IDCRx   indirect accessed DCR's
;       x = 1..4
;       the addr and data DCR is defined in the configuration file
;       e.g. IDCR1 0x010 0x011
; addr: the number, adddress or offset of the register
; size  the size of the register (8,16 or 32)
;
;name           type    addr            size
;-------------------------------------------
;
sp      GPR 1
;
;   Special Purpose Registers
;
xer             SPR     0x001
lr              SPR     0x008
ctr             SPR     0x009
dec             SPR     0x016
srr0            SPR     0x01a
srr1            SPR     0x01b
pid             SPR     0x030
decar           SPR     0x036
csrr0           SPR     0x03a
csrr1           SPR     0x03b
dear            SPR     0x03d
esr             SPR     0x03e
ivpr            SPR     0x03f
usprg0          SPR     0x100
sprg4r          SPR     0x104
sprg5r          SPR     0x105
sprg6r          SPR     0x106
sprg7r          SPR     0x107
tblr            SPR     0x10c
tbur            SPR     0x10d
sprg0           SPR     0x110
sprg1           SPR     0x111
sprg2           SPR     0x112
sprg3           SPR     0x113
sprg4w          SPR     0x114
sprg5w          SPR     0x115
sprg6w          SPR     0x116
sprg7w          SPR     0x117
tblw            SPR     0x11c
tbuw            SPR     0x11d
pir             SPR     0x11e
pvr             SPR     0x11f
dbsr            SPR     0x130
dbcr0           SPR     0x134
dbcr1           SPR     0x135
dbcr2           SPR     0x136
iac1            SPR     0x138
iac2            SPR     0x139
iac3            SPR     0x13a
iac4            SPR     0x13b
dac1            SPR     0x13c
dac2            SPR     0x13d
dvc1            SPR     0x13e
dvc2            SPR     0x13f
tsr             SPR     0x150
tcr             SPR     0x154
ivor0           SPR     0x190
ivor1           SPR     0x191
ivor2           SPR     0x192
ivor3           SPR     0x193
ivor4           SPR     0x194
ivor5           SPR     0x195
ivor6           SPR     0x196
ivor7           SPR     0x197
ivor8           SPR     0x198
ivor9           SPR     0x199
ivor10          SPR     0x19a
ivor11          SPR     0x19b
ivor12          SPR     0x19c
ivor13          SPR     0x19d
ivor14          SPR     0x19e
ivor15          SPR     0x19f
mcsrr0          SPR     0x23a
mcsrr1          SPR     0x23b
mcsr            SPR     0x23c
inv0            SPR     0x370
inv1            SPR     0x371
inv2            SPR     0x372
inv3            SPR     0x373
itv0            SPR     0x374
itv1            SPR     0x375
itv2            SPR     0x376
itv3            SPR     0x377
ccr1            SPR     0x378
dnv0            SPR     0x390
dnv1            SPR     0x391
dnv2            SPR     0x392
dnv3            SPR     0x393
dtv0            SPR     0x394
dtv1            SPR     0x395
dtv2            SPR     0x396
dtv3            SPR     0x397
dvlim           SPR     0x398
ivlim           SPR     0x399
rstcfg          SPR     0x39b
dcdbtrl         SPR     0x39c
dcdbtrh         SPR     0x39d
icdbtrl         SPR     0x39e
icdbtrh         SPR     0x39f
mmucr           SPR     0x3b2
ccr0            SPR     0x3b3
icdbdr          SPR     0x3d3
dbdr            SPR     0x3f3
;
;
;	Indirectly Accessed DCR's
;
;       IDCR1 must be set to SDRAM0_CFGADDR and SDRAM0_CFGDATA
;       IDCR2 must be set to EBC0_CFGADDR   and EBC0_CFGDATA
;       IDCR3 must be set to EBM0_CFGADDR   and EBM0_CFGDATA
;       IDCR4 must be set to PPM0_CFGADDR   and PPM0_CFGDATA
;       IDCR5 must be set to CPR0_CFGADDR   and CPR0_CFGDATA
;       IDCR6 must be set to SDR0_CFGADDR   and SDR0_CFGDATA
;
; External Bus Controller DCRs
;
ebc0_b0cr       IDCR2	0x00
ebc0_b1cr       IDCR2	0x01
ebc0_b2cr       IDCR2	0x02
ebc0_b3cr       IDCR2	0x03
ebc0_b4cr       IDCR2	0x04
ebc0_b5cr       IDCR2	0x05
ebc0_b6cr       IDCR2	0x06
ebc0_b7cr       IDCR2	0x07
ebc0_b0ap       IDCR2	0x10
ebc0_b1ap       IDCR2   0x11
ebc0_b2ap       IDCR2	0x12
ebc0_b3ap       IDCR2	0x13
ebc0_b4ap       IDCR2	0x14
ebc0_b5ap       IDCR2	0x15
ebc0_b6ap       IDCR2	0x16
ebc0_b7ap       IDCR2	0x17
ebc0_bear       IDCR2	0x20
ebc0_besr       IDCR2	0x21
ebc0_cfg        IDCR2	0x23
ebc0_cid        IDCR2	0x24
;
; Clocking and PowerOn Reset DCR
;
cpr0_clkupd     IDCR5   0x0020
cpr0_pllc       IDCR5	0x0040
cpr0_plld       IDCR5	0x0060
cpr0_plbed      IDCR5	0x0080
cpr0_plb2d      IDCR5	0x00A0
cpr0_opbd       IDCR5	0x00C0
cpr0_perd       IDCR5	0x00E0
cpr0_ahbd       IDCR5	0x0100
cpr0_icfg       IDCR5	0x0140
;
; System DCR
;
sdr0_sdstp0     IDCR6   0x0020
sdr0_sdstp1     IDCR6	0x0021
sdr0_pinstp     IDCR6	0x0040
sdr0_sdcs       IDCR6	0x0060
sdr0_ecid0      IDCR6	0x0080
sdr0_ecid1      IDCR6	0x0081
sdr0_ecid2      IDCR6	0x0082
sdr0_jtag       IDCR6	0x00C0
sdr0_ddrdl      IDCR6	0x00E0
sdr0_ebc        IDCR6	0x0100
sdr0_uart0      IDCR6	0x0120
sdr0_uart1      IDCR6	0x0121
sdr0_uart2      IDCR6	0x0122
sdr0_uart3      IDCR6	0x0123
sdr0_cp440      IDCR6	0x0180
sdr0_xcr        IDCR6	0x01C0
sdr0_xpllc      IDCR6	0x01C1
sdr0_xplld      IDCR6	0x01C2
sdr0_srst0      IDCR6	0x0200
sdr0_srst1      IDCR6	0x0201
sdr0_slpipe     IDCR6	0x0220
sdr0_amp        IDCR6	0x0240
sdr0_mirq0      IDCR6	0x0260
sdr0_mirq1      IDCR6	0x0261
sdr0_maltbl     IDCR6	0x0280
sdr0_malrbl     IDCR6	0x02A0
sdr0_maltbs     IDCR6	0x02C0
sdr0_malrbs     IDCR6	0x02E0
sdr0_pci0	IDCR6	0x0300
sdr0_usb2d0cr	IDCR6	0x0320
sdr0_usb2h0cr	IDCR6	0x0340
sdr0_cust0      IDCR6	0x4000
sdr0_sdstp2     IDCR6	0x4001
sdr0_cust1      IDCR6	0x4002
sdr0_sdstp3     IDCR6	0x4003
sdr0_pfc0       IDCR6	0x4100
sdr0_pfc1       IDCR6	0x4101
sdr0_usb2phy0cr IDCR6	0x4103
sdr0_plbtr      IDCR6	0x4200
sdr0_mfr        IDCR6	0x4300
sdr0_usb2host	IDCR6	0x4600
;
; Internal SRAM Controller
;
sram0_sb0cr     DCR     0x020
sram0_sb1cr     DCR     0x021
sram0_sb2cr     DCR     0x022
sram0_sb3cr     DCR     0x023
sram0_bear      DCR     0x024
sram0_besr0     DCR     0x025
sram0_besr1     DCR     0x026
sram0_pmeg      DCR     0x027
sram0_dpc       DCR     0x0a0
;
; Clock and Power Management
;
cpm0_er         DCR     0x160
cpm0_fr         DCR     0x161
cpm0_sr         DCR     0x162
;
; Double Data Rate (DDR) SDRAM Controller
;
mq0_b0bas       DCR     0x0040
mq0_b1bas       DCR     0x0041
mq0_b2bas       DCR     0x0042
mq0_b3bas       DCR     0x0043
mq0_cf1h        DCR     0x0045
mq0_esh         DCR     0x0047
mq0_eauh        DCR     0x0048
mq0_ealh        DCR     0x0049
mq0_baul	DCR     0x004A
mq0_cf1l	DCR     0x004B
mq0_esl		DCR     0x004C
mq0_eaul	DCR     0x004D
mq0_eall	DCR     0x004E
mq0_cfbhl	DCR     0x004F
mq0_bauh	DCR     0x0050
;
mcif0_mcstat	IDCR1   0x0014
mcif0_mcopt1	IDCR1	0x0020
mcif0_mcopt2	IDCR1	0x0021
mcif0_modt0	IDCR1	0x0022
mcif0_modt1	IDCR1	0x0023
mcif0_modt2	IDCR1	0x0024
mcif0_modt3	IDCR1	0x0025
mcif0_codt	IDCR1	0x0026
mcif0_vvpr	IDCR1	0x0027
mcif0_opar1	IDCR1	0x0028
;mcif0_opar2	IDCR1	0x0029
mcif0_rtr	IDCR1	0x0030
mcif0_mb0cf	IDCR1	0x0040
mcif0_mb1cf	IDCR1	0x0044
mcif0_mb2cf	IDCR1	0x0048
mcif0_mb3cf	IDCR1	0x004C
mcif0_initplr0	IDCR1	0x0050
mcif0_initplr1	IDCR1	0x0051
mcif0_initplr2	IDCR1	0x0052
mcif0_initplr3	IDCR1	0x0053
mcif0_initplr4	IDCR1	0x0054
mcif0_initplr5	IDCR1	0x0055
mcif0_initplr6	IDCR1	0x0056
mcif0_initplr7	IDCR1	0x0057
mcif0_initplr8	IDCR1	0x0058
mcif0_initplr9	IDCR1	0x0059
mcif0_initplr10	IDCR1	0x005A
mcif0_initplr11	IDCR1	0x005B
mcif0_initplr12	IDCR1	0x005C
mcif0_initplr13	IDCR1	0x005D
mcif0_initplr14	IDCR1	0x005E
mcif0_initplr15	IDCR1	0x005F
mcif0_rqdc 	IDCR1	0x0070
mcif0_rfdc 	IDCR1	0x0074
mcif0_rdcc      IDCR1	0x0078
mcif0_dlcr	IDCR1	0x007A
mcif0_clktr	IDCR1	0x0080
mcif0_wrdtr	IDCR1	0x0081
mcif0_sdtr1	IDCR1	0x0085
mcif0_sdtr2	IDCR1	0x0086
mcif0_sdtr3	IDCR1	0x0087
mcif0_mmode	IDCR1	0x0088
mcif0_memode	IDCR1	0x0089
mcif0_ecces	IDCR1	0x0098
mcif0_fcsr	IDCR1	0x00B0
mcif0_rtsr	IDCR1	0x00B1
;
;
; Memory Mapped Peripherals
; =========================
;
; PMM1 must point to Peripheral space (real 4_0000_0000)
;
; GPIO
;
gpio0_or        PMM1    0xEF600B00
gpio0_tcr       PMM1    0xEF600B04
gpio0_osrl      PMM1    0xEF600B08
gpio0_osrh      PMM1    0xEF600B0C
gpio0_tsrl      PMM1    0xEF600B10
gpio0_tsrh      PMM1    0xEF600B14
gpio0_odr       PMM1    0xEF600B18
gpio0_ir        PMM1    0xEF600B1C
gpio0_rr1       PMM1    0xEF600B20
gpio0_rr2       PMM1    0xEF600B24
gpio0_rr3       PMM1    0xEF600B28
gpio0_isr1l     PMM1    0xEF600B30
gpio0_isr1h     PMM1    0xEF600B34
gpio0_isr2l     PMM1    0xEF600B38
gpio0_isr2h     PMM1    0xEF600B3C
gpio0_isr3l     PMM1    0xEF600B40
gpio0_isr3h     PMM1    0xEF600B44
;
gpio1_or        PMM1    0xEF600C00
gpio1_tcr       PMM1    0xEF600C04
gpio1_osrl      PMM1    0xEF600C08
gpio1_osrh      PMM1    0xEF600C0C
gpio1_tsrl      PMM1    0xEF600C10
gpio1_tsrh      PMM1    0xEF600C14
gpio1_odr       PMM1    0xEF600C18
gpio1_ir        PMM1    0xEF600C1C
gpio1_rr1       PMM1    0xEF600C20
gpio1_rr2       PMM1    0xEF600C24
gpio1_rr3       PMM1    0xEF600C28
gpio1_isr1l     PMM1    0xEF600C30
gpio1_isr1h     PMM1    0xEF600C34
gpio1_isr2l     PMM1    0xEF600C38
gpio1_isr2h     PMM1    0xEF600C3C
gpio1_isr3l     PMM1    0xEF600C40
gpio1_isr3h     PMM1    0xEF600C44
;


