;bdiGDB configuration file for P5020-DS
;--------------------------------------
;
;
[INIT]
;
;WREG    MSR                     0x80001002              ;set 64-bit mode
;
; Setup TLB1
;          MAS1       MAS2       MAS0/MAS7     MAS3
WTLB    0x80000700_0xfe00000a   0x10010000_0xfe00003f   ;1/1: fe000000->0_fe000000  16MB -I-G- RWXRWX
WTLB    0x80000900_0xe000000a   0x10020000_0xe000003f   ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX
WTLB    0x80000a00_0x00000000   0x10030000_0x0000003f   ;1/3: 00000000->0_00000000   1GB ----- RWXRWX
WTLB    0x80000a00_0x40000000   0x10040000_0x4000003f   ;1/4: 40000000->0_40000000   1GB ----- RWXRWX
WTLB    0x80000500_0x80000000   0x10050000_0x8000003f   ;1/5: 80000000->0_80000000   1MB ----- RWXRWX
;
;WREG    MAS2                    0x00000064_0x00000000   ;set MAS2 upper word
;WTLB    0x80000700_0xff00000a   0x10060000_0xff00003f   ;1/1: 64_ff000000->0_ff000000  16MB -I-G- RWXRWX
;
;=========================================================================================
; Setup TLB0 (for test purpose only)
;          MAS1       MAS2       MAS0/MAS7     MAS3
WTLB    0x80000100_0xc0000000   0x00000000_0x0000003f   ;WAY0: c0000000->0_00000000   4KB ----- RWXRWX
WTLB    0x80000100_0xc0001000   0x00000000_0x0000103f   ;WAY0: c0001000->0_00001000   4KB ----- RWXRWX
WTLB    0x80000100_0xc0002000   0x00000000_0x0000203f   ;WAY0: c0002000->0_00002000   4KB ----- RWXRWX
WTLB    0x80000100_0xc0003000   0x00000000_0x0000303f   ;WAY0: c0003000->0_00003000   4KB ----- RWXRWX
;=========================================================================================
;
; Initialize LAWBAR's
WM32    0xfe000c00      0x00000000      ;LAWBAR0 : Flash @0_e0000000
WM32    0xfe000c04      0xe0000000
WM32    0xfe000c08      0x81f0001b      ;LAWAR0  : eLBC 256MB
;
WM32    0xfe000c10      0x00000000      ;LAWBAR1 : CPC1/SRAM @0_80000000
WM32    0xfe000c14      0x80000000
WM32    0xfe000c18      0x81000013      ;LAWAR1  : DDR1/CPC1 1MB
;
WM32    0xfe000df0      0x00000000      ;LAWBAR31: SDRAM @0_00000000
WM32    0xfe000df4      0x00000000
WM32    0xfe000df8      0x8100001e      ;LAWAR31 : DDR1/CPC1 2GB
;
; Use L3 cache (CPC1) as SRAM at 0x80000000
WM32    0xfe010100      0x00000000      ;CPC1_SRCR1 : high address
WM32    0xfe010104      0x8000000b      ;CPC1_SRCR0 : all 32 ways as SRAM
WM32    0xfe010000      0x80000000      ;CPC1_CSR0  : CPC enable
WM32    0xfe010f00      0x08000000      ;CPC1_HDBCR0: Speculation disable
;
; Local Bus Controller
WM32    0xfe124004      0xf8000ff7      ;OR0:
WM32    0xfe124000      0xe8001001      ;BR0:
WM32    0xfe12400c      0xf8000ff7      ;OR1:
WM32    0xfe124008      0xe0001001      ;BR1:
;


[TARGET]
; common parameters
POWERUP     5000                ;start delay after power-up detected in ms
JTAGCLOCK   2                   ;use 4 MHz JTAG clock
RESET       HARD  500           ;assert reset for 0.5 seconds
WAKEUP      200                 ;give reset time to complete
;MEMACCESS   SAP  10             ;memory access via SAP (10us access delay)
;
;========================================================
; !!!! define the core ID (the #x) without any holes !!!!
; !!!! no need that core ID matches the core number  !!!!
; !!!! A valid example is: #1 CPUTYPE  P4080 5 0     !!!!
;========================================================
;
; CoreID#0 parameters (active vCPU after reset)
#0 CPUTYPE      P5020 0 0       ;Core#0 / SOC#0
#0 EDBCR0       EDM DNH EFT     ;set run parameters
#0 STARTUP      HALT            ;halt at the reset vector (this halts all cores !!!)
#0 BREAKMODE    SOFT            ;SOFT or HARD, HARD uses PPC hardware breakpoint
#0 STEPMODE     HWBP            ;ICMP or HWBP, HWBP uses a hardware breakpoint
#0 REGLIST      STD FPR 64BIT   ;use GDB 64-bit register packet
;
;
; CoreID#1 parameters
#1 CPUTYPE      P5020 1 0       ;Core#1 / SOC#0
#1 EDBCR0       EDM DNH EFT     ;set run parameters
#1 STARTUP      HALT            ;halt at the reset vector
;


[HOST]
IP              151.120.25.119
FILE            E:\temp\dump256k.bin
FORMAT          BIN 0x80000000
;
#0 PROMPT       P5020#0>
#1 PROMPT       P5020#1>
;

[FLASH]
;flash is S29GL01GP
WORKSPACE   0x80001000          ;workspace in CPC1/SRAM
CHIPTYPE    MIRRORX16           ;Flash type is S29GL01GP
CHIPSIZE    0x08000000          ;The size of one flash chip in bytes
BUSWIDTH    16                  ;The width of the flash memory bus in bits
FILE        E:\temp\dump256k.bin
FORMAT      BIN 0xed800000
ERASE       0xed800000 0x20000 4


[REGS]
FILE        $regP5020.def