;Register definition for PPC750FX / CPC700
;=======================================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	SPR	special purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
;	IMMx	indirect memory mapped register
;		x = 1..4
;		the addr and data address is defined in the configuration file
;		e.g. IMM1 0xFEC00000 0xFEE00000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
sp		GPR	1
;
xer		SPR	1
lr		SPR	8
ctr		SPR	9
dsisr           SPR     18
dar             SPR     19
dec             SPR     22
sdr1            SPR     25
srr0            SPR     26
srr1            SPR     27
;
tbl             SPR     268
tbu             SPR     269
sprg0		SPR	272
sprg1		SPR	273
sprg2		SPR	274
sprg3		SPR	275
ear             SPR     282
pvr             SPR     287
;
ibat0u          SPR     528
ibat0l          SPR     529
ibat1u          SPR     530
ibat1l          SPR     531
ibat2u          SPR     532
ibat2l          SPR     533
ibat3u          SPR     534
ibat3l          SPR     535
;
ibat4u          SPR     560
ibat4l          SPR     561
ibat5u          SPR     562
ibat5l          SPR     563
ibat6u          SPR     564
ibat6l          SPR     565
ibat7u          SPR     566
ibat7l          SPR     567
;
dbat0u          SPR     536
dbat0l          SPR     537
dbat1u          SPR     538
dbat1l          SPR     539
dbat2u          SPR     540
dbat2l          SPR     541
dbat3u          SPR     542
dbat3l          SPR     543
;
dbat4u          SPR     568
dbat4l          SPR     569
dbat5u          SPR     570
dbat5l          SPR     571
dbat6u          SPR     572
dbat6l          SPR     573
dbat7u          SPR     574
dbat7l          SPR     575
;
mmcr0           SPR     952
pmc1            SPR     953
pmc2            SPR     954
sia             SPR     955
mmcr1           SPR     956
pmc3            SPR     957
pmc4            SPR     958
;
hid0            SPR     1008
hid1            SPR     1009
;
iabr            SPR     1010
dabr            SPR     1013
l2cr            SPR     1017
ictc            SPR     1019
thrm1           SPR     1020
thrm2           SPR     1021
thrm3           SPR     1022
;
;
; IMM1 must be set to the processor interface configuration registers
;
prifopt1        IMM1    0x00    32
errdet1         IMM1    0x04    32
erren1          IMM1    0x08    32
cpuerad         IMM1    0x0c    32
cpuerat         IMM1    0x10    32
plbmifopt       IMM1    0x18    32
plbmtlsa1       IMM1    0x20    32
plbmtlea1       IMM1    0x24    32
plbmtlsa2       IMM1    0x28    32
plbmtlea2       IMM1    0x2c    32
plbmtlsa3       IMM1    0x30    32
plbmtlea3       IMM1    0x34    32
plbsnssa0       IMM1    0x38    32
plbsnsea0       IMM1    0x3c    32
besr            IMM1    0x40    32
besrset         IMM1    0x44    32
bear            IMM1    0x4c    32
plbswrint       IMM1    0x80    32
;
;
; IMM2 must be set to the memory controller configuration registers
;
mcopt1          IMM2    0x20    32
mben            IMM2    0x24    32
memtype         IMM2    0x28    32
rwd             IMM2    0x2c    32
rtr             IMM2    0x30    32
dam             IMM2    0x34    32
mb0sa           IMM2    0x38    32
mb1sa           IMM2    0x3c    32
mb2sa           IMM2    0x40    32
mb3sa           IMM2    0x44    32
mb4sa           IMM2    0x48    32
mb0ea           IMM2    0x58    32
mb1ea           IMM2    0x5c    32
mb2ea           IMM2    0x60    32
mb3ea           IMM2    0x64    32
mb4ea           IMM2    0x68    32
sdtr1           IMM2    0x80    32
rbw             IMM2    0x88    32
fwen            IMM2    0x90    32
ecccf           IMM2    0x94    32
eccerr          IMM2    0x98    32
rpb0p           IMM2    0xe0    32
rpb1p           IMM2    0xe4    32
rpb2p           IMM2    0xe8    32
rpb3p           IMM2    0xec    32
rpb4p           IMM2    0xf0    32
;
;
