; bdiWind configuration file for Wind River MdpPro850 128 MB SDRAM Evaluation board ; --------------------------------------------------------------------------------- ; [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI WSPR 27 0x00001002 ;SRR1 : ME,RI ;WSPR 149 0x2002000F ;DER : set debug enable register WSPR 149 0x2006000F ;DER : enable SYSIE for BDI flash progr. WSPR 638 0xFF000000 ;IMMR : internal memory at 0xFF000000 WSPR 158 0x00000007 ;ICTRL: ; init SIU register WM32 0xFF000000 0x01632440 ;SIUMCR 0x01610400 WM32 0xFF000004 0xFFFFFF88 ;SYPCR WM16 0xFF000200 0x0002 ;TBSCR WM32 0xFF000320 0x55CCAA33 ;RTCSCK: unlock real-time clock status and control register WM16 0xFF000220 0x0102 ;RTCSC WM16 0xFF000240 0x0002 ;PTSCR WM32 0xFF000284 0x00900000 ;PLPRCR no need to change (1:1 clock mode) 0x00900000 ; init UPM ; SUPM 0xFF000168 0xFF00017c ;set address for MCR and MDR 0xFF00017c ; ; single read. (offset 0 in UPMA RAM) ; WUPM 0x00000000 0x0ff0fc04 ;UPMA single read WUPM 0x00000001 0x0ff0fc00 WUPM 0x00000002 0x1ff7fc07 WUPM 0x00000003 0xffffffff WUPM 0x00000004 0xffffffff ;last ; ; SDRAM initialization (offset 5 in UPMA RAM) ; WUPM 0x00000005 0xffffffff WUPM 0x00000006 0xffffffff WUPM 0x00000007 0xffffffff ;last ; ; burst read. (offset 8 in UPMA RAM) ; WUPM 0x00000008 0x0ff3fc04 WUPM 0x00000009 0x0ff3fc00 WUPM 0x0000000A 0x0ff3fc0c WUPM 0x0000000B 0x0ff3fc00 WUPM 0x0000000C 0x0ff3fc0c WUPM 0x0000000D 0x0ff3fc00 WUPM 0x0000000E 0x0ff3fc0c WUPM 0x0000000F 0x0ff3fc00 ;last WUPM 0x00000010 0x1ff7fc07 WUPM 0x00000011 0xffffffff WUPM 0x00000012 0xffffffff WUPM 0x00000013 0xffffffff WUPM 0x00000014 0xffffffff WUPM 0x00000015 0xffffffff WUPM 0x00000016 0xffffffff WUPM 0x00000017 0xffffffff ; ; single write. (offset 18 in UPMA RAM) ; WUPM 0x00000018 0x0cfffc04 WUPM 0x00000019 0x00fffc00 WUPM 0x0000001A 0x13fffc07 WUPM 0x0000001B 0xffffffff ;last WUPM 0x0000001C 0xffffffff WUPM 0x0000001D 0xffffffff WUPM 0x0000001E 0xffffffff WUPM 0x0000001F 0xffffffff ; ; burst write. (offset 20 in UPMA RAM) ; WUPM 0x00000020 0x0fffcc04 WUPM 0x00000021 0x00fffc00 WUPM 0x00000022 0x0ffffc0c WUPM 0x00000023 0x00fffc00 WUPM 0x00000024 0x0ffffc0c WUPM 0x00000025 0x00fffc00 WUPM 0x00000026 0x0ffffc0c ;last WUPM 0x00000027 0x00fffc00 WUPM 0x00000028 0xfffffc07 WUPM 0x00000029 0xffffffff WUPM 0x0000002A 0xffffffff WUPM 0x0000002B 0xffffffff WUPM 0x0000002C 0xffffffff WUPM 0x0000002D 0xffffffff WUPM 0x0000002E 0xffffffff WUPM 0x0000002F 0xffffffff ; ; refresh (offset 30 in UPMA RAM) ; WUPM 0x00000030 0xffffffff WUPM 0x00000031 0xffffffff WUPM 0x00000032 0xffffffff WUPM 0x00000033 0xffffffff WUPM 0x00000034 0xffffffff WUPM 0x00000035 0xffffffff ;last WUPM 0x00000036 0xffffffff WUPM 0x00000037 0xffffffff WUPM 0x00000038 0xffffffff WUPM 0x00000039 0xffffffff WUPM 0x0000003A 0xffffffff WUPM 0x0000003B 0xffffffff ; ; exception. (offset 3c in UPMA RAM) ; WUPM 0x0000003C 0xffffffff ;last WUPM 0x0000003D 0xFFFFFFFF WUPM 0x0000003E 0xFFFFFFFF WUPM 0x0000003F 0xFFFFFFFF ;***************************************************************************** ; UPM B ;***************************************************************************** WUPM 0x00800000 0xCF0BFC24 WUPM 0x00800001 0x0C26FC04 WUPM 0x00800002 0x03B9BC04 WUPM 0x00800003 0x0FF77C00 WUPM 0x00800004 0x3FFFFC45 WUPM 0x00800005 0xFFFFFFFF WUPM 0x00800006 0xFFFFFFFF WUPM 0x00800007 0xFFFFFFFF WUPM 0x00800008 0xCF0BFC24 WUPM 0x00800009 0x0C26FC04 WUPM 0x0080000A 0x00ACFC0C WUPM 0x0080000B 0x00ACFC08 WUPM 0x0080000C 0x00ACFC08 WUPM 0x0080000D 0x03B9BC00 WUPM 0x0080000E 0x0FF77C00 WUPM 0x0080000F 0x3FFFFC45 WUPM 0x00800010 0x08FFCC00 WUPM 0x00800011 0x33FFCC47 WUPM 0x00800012 0xFFFFFFFF WUPM 0x00800013 0xFFFFFFFF WUPM 0x00800014 0xCFCFB834 WUPM 0x00800015 0x3F357404 WUPM 0x00800016 0xFFFFFC05 WUPM 0x00800017 0xFFFFFFFF WUPM 0x00800018 0xCF0BFC24 WUPM 0x00800019 0x0C26BC00 WUPM 0x0080001A 0x03AC3C04 WUPM 0x0080001B 0x1FA74024 WUPM 0x0080001C 0xFFFFFC05 WUPM 0x0080001D 0xFFFFFFFF WUPM 0x0080001E 0xFFFFFFFF WUPM 0x0080001F 0xFFFFFFFF WUPM 0x00800020 0xCF0BF024 WUPM 0x00800021 0x0806BC00 WUPM 0x00800022 0x000C3C00 WUPM 0x00800023 0x000FFC00 WUPM 0x00800024 0x000FFC00 WUPM 0x00800025 0x000FFC04 WUPM 0x00800026 0x10077C05 WUPM 0x00800027 0xFFFFFFFF WUPM 0x00800028 0xF7FFCC04 WUPM 0x00800029 0xFFFFCC46 WUPM 0x0080002A 0xFFFFFFFF WUPM 0x0080002B 0xFFFFFFFF WUPM 0x0080002C 0xFFFFFFFF WUPM 0x0080002D 0xFFFFFFFF WUPM 0x0080002E 0xFFFFFFFF WUPM 0x0080002F 0xFFFFFFFF WUPM 0x00800030 0xCFFBBC04 WUPM 0x00800031 0x0FF27C04 WUPM 0x00800032 0x3FF5FC04 WUPM 0x00800033 0xFFFFFC04 WUPM 0x00800034 0xFFFFFC05 WUPM 0x00800035 0xFFFFFFFF WUPM 0x00800036 0xFFFFFFFF WUPM 0x00800037 0xFFFFFFFF WUPM 0x00800038 0xFFFFFFFF WUPM 0x00800039 0xFFFFFFFF WUPM 0x0080003A 0xFFFFFFFF WUPM 0x0080003B 0xFFFFFFFF WUPM 0x0080003C 0xFFFFFC05 WUPM 0x0080003D 0xFFFFFFFF WUPM 0x0080003E 0xFFFFFFFF WUPM 0x0080003F 0xFFFFFFFF WM32 0xFF000170 0x61B20111 ; MAMR = machine A mode register WM32 0xFF000174 0x27A06111 ; MBMR = machine B mode register ;***************************************************************************** ; Init Memory Controller: ; WM32 0xFF000104 0xFFC00760 ;OR0 WM32 0xFF000100 0xFFC00001 ;BR0 WM32 0xFF00010C 0x00000000 ;OR1 WM32 0xFF000108 0x00000000 ;BR1 WM32 0xFF000114 0xFC000800 ;OR2 WM32 0xFF000110 0x000000C1 ;BR2 WM32 0xFF00011C 0xF8000800 ;OR3 WM32 0xFF000118 0x040000C1 ;BR3 WM32 0xFF000124 0xFFF80010 ;OR4 WM32 0xFF000120 0x04000080 ;BR4 not valid because of 128M on CS 2-3 WM32 0xFF00012C 0xFFFF8760 ;OR5 WM32 0xFF000128 0x10000401 ;BR5 WM32 0xFF000134 0x00000000 ;OR6 WM32 0xFF000130 0x00000000 ;BR6 WM32 0xFF00013C 0x00000000 ;OR7 WM32 0xFF000138 0x00000000 ;BR7 ; Initialize memory periodic timer prescaler (MPTPR). ; Preliminary prescaler for refresh (depends on number of banks). ; This value is selected for four cycles every 62.4 us with two SDRAM ; banks or four cycles every 31.2 us with one bank. It will be adjusted ; after memory sizing. WM16 0xFF00017A 0x0200 WM32 0xFF000164 0x00000088 ; MAR = Memory Address Register ;WM32 0xFF000164 0x04000088 ; MAR = Memory Address Register ; Execute precharge-all command using Memory Command Register, Patch-Offset 5. ; Immediately following initialize SDRAM starting at Patch-Offset 7. ; ; Banks 0 and 1 on CS2, CS3 WM32 0xFF000168 0x80804105 WM32 0xFF000168 0x80806105 ; ; 2 x 4fach-Refresh durchführen über Memory Command Register an Patch-Offset $30 ; WM32 0xFF000168 0x80804130 WM32 0xFF000168 0x80804130 WM32 0xFF000168 0x80806130 WM32 0xFF000168 0x80806130 WM32 0xFF000164 0x00000088 ; MAR = Memory Address Register WM32 0xFF000168 0x80804114 WM32 0xFF000168 0x80804114 WM32 0xFF000168 0x80806114 WM32 0xFF000168 0x80806114 [TARGET] ;CPUTYPE MPC800 CPUCLOCK 50000000 ;the CPU clock rate after processing the init list BDIMODE GATEWAY ;the BDI working mode (LOADONLY | AGENT | GATEWAY) ;INITTIME 80 ; timeout ;BREAKMODE SOFT ; SOFT or HARD, HARD uses PPC hardware breakpoints ;STEPMODE HWBP ; TRACE or HWBP, HWPB uses one or two hardware breakpoints MEMBASE 0 ; base of target memory MEMSIZE 0x08000000 ; size of target memory POOLBASE 0x00300000 ; base of host controlled target memory POOLSIZE 0x00100000 ; size of host controlled target memory [HOST] IP 139.79.205.105 FILE D:\Tornado2.2\target\config\wrMdpPro8xx.bdi\vxWorks FORMAT ELF LOAD AUTO ;load code MANUAL or AUTO after reset ;START 0x00100000 [FLASH] ;CHIPTYPE AM29F ;Flash type (AM29LV160B) ;CHIPSIZE 0x200000 ;The size of one flash chip in bytes ;BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0xFF002000 ; RAM buffer for fast flash programming ;FILE /tftpboot/ppcboot.bin ;The file to program ;FORMAT BIN 0x40000000 ;ERASE 0x40000000 BLOCK ;ERASE 0x40008000 BLOCK ;ERASE 0x4000C000 BLOCK ;ERASE 0x40010000 BLOCK