; bdiGDB configuration file for Alchemy AU1000
; --------------------------------------------
; This configuration lets the monitor setup the board.
;
[INIT]
;
WCP0    12          0x00000000  ;disable interrupts
;
; Setup Static Bus Controller (16Mbyte at 0xbe000000)
WM32    0xB4001000  0x00000043  ;RCS0 Configuration
;WM32	0xB4001004  0x040181D7	;RCS0 Timing
WM32    0xB4001008  0x11F03FC0  ;RCS0 Address
;
; Setup Endianess
WM32    0xB1900038  0x00000001  ;Set to Little Endian
WCP0    16          0x00000003
;


[TARGET]
JTAGCLOCK   8000000   		;use 8 MHz JTAG clock
CPUTYPE     AU1000	        ;the used target CPU family
ENDIAN      LITTLE              ;target is little endian
STARTUP     HALT                 ;halt at the reset vector
;STARTUP     RUN                 ;let YAMON run
RESET       JTAG		;the reset type (NONE, JTAG, HARD)

; Apply a hard reset
SCANINIT    r1:w10000:t0:w100000:       ;toggle RESET
SCANINIT    t1:w1000:t0:w1000:          ;toggle TRST
SCANINIT    ch10:w1000:                 ;clock TCK with TMS high


[HOST]
PROMPT      AU1000>


[FLASH]
CHIPTYPE	MIRRORX16       ;there is a MirrorBit flash in x16 mode
CHIPSIZE	0x01000000      ;the chip is S29GL128P
;CHIPTYPE	AM29BX16         ;there is an AMD flash in x16 mode
;CHIPSIZE	0x00800000       ;the chip is Am29LV642
BUSWIDTH	16              ;only one chip for a 16-bit system


[REGS]
DMM1	0xB4000000      ;memory controller base address
DMM2	0xB0400000      ;interrupt controller 0 base address
DMM3	0xB1800000      ;interrupt controller 1 base address
FILE	$regau1000.def