; bdiGDB configuration file for PMC-Sierra MSP7120 board
; ------------------------------------------------------
;
; This configuration uses the monitor setup the board
;
[INIT]
; Setup TLB
;WTLB    0x00000700  0x01E00017  ;Monitor Flash 2 x 16MB, uncached DVG
;
; Invalidate Caches
;IVIC                            ;Invalidate IC
;IVDC                            ;Invalidate DC


[TARGET]
JTAGCLOCK   0                   ;use 16 MHz JTAG clock
POWERUP     2000                ;power-up delay
WAKEUP      100                 ;delay after releasing reset

; VPE0
#0 CPUTYPE     M34K             ;the used target CPU type
#0 ENDIAN      BIG              ;target is big endian
#0 STARTUP     RESET            ;halt VPE at the reset vector
#0 BREAKMODE   SOFT        	;SOFT or HARD, HARD uses hardware breakpoints
#0 STEPMODE    JTAG             ;JTAG, HWBP or SWBP
#0 SCANPRED    0 0              ;no  device before
#0 SCANSUCC    1 5              ;one device after

; VPE1
#1 CPUTYPE     M34K             ;the used target CPU type
#1 ENDIAN      BIG              ;target is big endian
#1 STARTUP     RUN              ;don't halt VPE1, is not active out of reset
#1 BREAKMODE   SOFT        	;SOFT or HARD, HARD uses hardware breakpoints
#1 STEPMODE    JTAG             ;JTAG, HWBP or SWBP
#1 SCANPRED    1 5              ;one device before
#1 SCANSUCC    0 0              ;no  device after


[HOST]
IP          151.120.25.119
FILE        E:\cygwin\home\demo\mips\fibo.x
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
#0 PROMPT   VPE0>
#1 PROMPT   VPE1>


[FLASH]


[REGS]
#0 DMM1     0xFF300000      ;DSU base address
#0 FILE     $reg34k.def
#1 DMM1     0xFF300000      ;DSU base address
#1 FILE     $reg34k.def