; bdiGDB configuration file for Alchemy DB1100 board
; --------------------------------------------------
;
; Commands supported in the SCANINIT string:
;
;  I<n>=<...b2b1b0>   write IR, b0 is first scanned
;  D<n>=<...b2b1b0>   write DR, b0 is first scanned
;                       n  : the number of bits 1..256
;                       bx : a data byte, two hex digits
;  W<n>               wait for n (decimal) micro seconds
;  T1                 assert TRST
;  T0                 release TRST
;  R1                 assert RESET
;  R0                 release RESET
;  CH<n>              clock TCK n (decimal) times with TMS high
;  CL<n>              clock TCK n (decimal) times with TMS low
;
;
[INIT]
;
WREG    status          0x00000000  ;disable interrupts
WREG    sys_scratch0    0x12345678
;
; Setup CPU PLL to 396 MHz
WREG    sys_cpupll      0x00000021  ;CPU_PLL Configuration
DELAY   100
;
; Setup Endianess
WREG    sys_endian      0x00000001  ;Set to Little Endian
WREG    config          0x00000003
;
; Setup Static Bus Controller
WREG    mem_stcfg0      0x00000003  ;RCS0 Configuration
WREG	mem_sttime0     0x040181D7  ;RCS0 Timing
WREG    mem_staddr0     0x11E03F80  ;RCS0 Address
WREG    mem_stcfg1      0x00000080  ;RCS1 Configuration
WREG    mem_sttime1     0x22080a20  ;RCS1 Timing
WREG    mem_staddr1     0x10c03f00  ;RCS1 Address
;WREG    mem_stcfg2      0x00000000  ;RCS2 Configuration
;WREG    mem_sttime2     0x00000000  ;RCS2 Timing
;WREG    mem_staddr2     0x00000000  ;RCS2 Address
WREG    mem_stcfg3      0x00000002  ;RCS3 Configuration
WREG    mem_sttime3     0x280E3E07  ;RCS3 Timing
WREG    mem_staddr3     0x10000000  ;RCS3 Address
;
; Setup SDRAM Controller
WREG    mem_sdmode0     0x005522AA  ;CS0 mode configuration
WREG    mem_sdmode1     0x005522AA  ;CS1 mode configuration
WREG    mem_sdmode2     0x00000000  ;CS2 mode configuration
WREG    mem_sdaddr0     0x001003F8  ;CS0 address, 32MB at 0x00000000
WREG    mem_sdaddr1     0x001023F8  ;CS1 address, 32MB at 0x02000000
WREG    mem_sdaddr2     0x00000000  ;CS2 address,
WREG    mem_sdrefcfg    0x64000C24  ;Program refresh (disabled)
WREG    mem_sdprecmd    0x00000000  ;Precharge all banks
WREG    mem_sdautoref   0x00000000  ;Issue two auto refreshes
WREG    mem_sdautoref   0x00000000  ;Issue two auto refreshes
WREG    mem_sdrefcfg    0x66000C24  ;Enable refresh
WREG    mem_sdwrmd0     0x00000033  ;CS0 set mode
WREG    mem_sdwrmd1     0x00000033  ;CS1 set mode
WREG    mem_sdwrmd2     0x00000000  ;CS2 set mode
;

[TARGET]
JTAGCLOCK   4000000             ;use 16 MHz JTAG clock
CPUTYPE     AU1000	        ;the used target CPU type
ENDIAN      LITTLE              ;target is little endian
RESET       HARD 200		;the reset type (NONE, JTAG, HARD)
WORKSPACE   0xA0000080	        ;workspace in target RAM for fast download
BREAKMODE   SOFT          	;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE    JTAG                ;JTAG, HWBP or SWBP
VECTOR      CATCH               ;catch unhandled exceptions
POWERUP     5000		;power-up delay 5 seconds
;WAKEUP      500

[HOST]
FILE        E:\cygwin\home\bdidemo\mips\fibo.x
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
PROMPT      DB1100>


[FLASH]
; measured programming speed 50 kBytes/sec
WORKSPACE	0xA0001000;
CHIPTYPE	MIRRORX16       ;there is a MirrorBit flash in x16 mode
;CHIPTYPE	AM29BX16       ;there is a MirrorBit flash in x16 mode
CHIPSIZE	0x800000        ;the chip is Am29LV640MH
BUSWIDTH	32              ;there are two chips building a 32-bit system
;FILE		E:\cygwin\home\bdidemo\mips\db1100.bin
;FORMAT		BIN 0xBFC80000;
FILE		E:\temp\dump512k.bin
FORMAT		BIN 0xBFC80000;
;ERASE		0xBFC80000;
;ERASE		0xBFCA0000;
;ERASE		0xBFCC0000;
;ERASE		0xBFCE0000;
ERASE		0xBFC80000 0x20000 8 ;erase 8 sectors

[REGS]
DMM1	0xB4000000      ;memory controller base address
DMM2	0xB0400000      ;interrupt controller 0 base address
DMM3	0xB1800000      ;interrupt controller 1 base address
FILE	$regau1k.def