;Register definition for Manzano core ;==================================== ; ; name: user defined name of the register (max. 15 characters) ; type: the type of the register ; GPR general purpose register ; CP15 CP15 register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ; ; CP15 Registers Numbers for xScale: ; ; +-----+-+-------+-----+-+-------+ ; |opc_2|0| CRm |opc_1|0| nbr | ; +-----+-+-------+-----+-+-------+ ; 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ; 1 1 1 1 1 1 ; ; The 16bit register number is used to build the appropriate MCR/MRC instruction. ; ; ;name type addr size ;------------------------------------------- ; id CP15 0x0000 32 ;Main ID ctype CP15 0x2000 32 ;L1 Cache type l2id CP15 0x0020 32 ;L2 System ID l2ctype CP15 0x2020 32 ;L2 System ID ctrl CP15 0x0001 32 ;Control auxctrl CP15 0x2001 32 ;Auxiliary Control ttbase CP15 0x0002 32 ;Translation Table Base dacr CP15 0x0003 32 ;Domain Access Control fsr CP15 0x0005 32 ;Fault Status far CP15 0x0006 32 ;Fault Address pid CP15 0x000d 32 ;Process ID cpar CP15 0x010f 32 ;Coprocessor Access ; pmnc CP14 0x0100 32 ;Performance Monitor Control ccnt CP14 0x0101 32 ;Performance Monitor Clock Counter inten CP14 0x0104 32 ;Interrupt Enable flag CP14 0x0105 32 ;Overflow Flag evtsel CP14 0x0108 32 ;Event Selection pmn0 CP14 0x0200 32 ;Performance Count Register 0 pmn1 CP14 0x0201 32 ;Performance Count Register 1 pmn2 CP14 0x0202 32 ;Performance Count Register 2 pmn3 CP14 0x0203 32 ;Performance Count Register 3 cclkcfg CP14 0x0006 32 ;Core Clock Configuration pwrmode CP14 0x0007 32 ;Power Mode ;