;Register definition for IXP435
;==============================
;
; name: user defined name of the register (max. 15 characters)
; type: the type of the register
;       GPR     general purpose register
;       CP15    CP15 register
;       MM      memory mapped register
;       DMMx    direct memory mapped register with offset
;               x = 1..4
;               the base is defined in the configuration file
;               e.g. DMM1 0x02200000
; addr: the number, adddress or offset of the register
; size  the size of the register (8,16 or 32)
;
;
; CP15 Registers Numbers for xScale:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;        5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
;        1 1 1 1 1 1
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name           type    addr            size
;-------------------------------------------
;
id              CP15    0x0000          32      ;ID code
cache           CP15    0x2000          32      ;Cache type
ctr             CP15    0x0001          32      ;Control
aux             CP15    0x2001          32      ;Auxiliary Control
ttb             CP15    0x0002          32      ;Translation Table Base
dac             CP15    0x0003          32      ;Domain Access Control
fsr             CP15    0x0005          32      ;Fault Status
far             CP15    0x0006          32      ;Fault Address
pid             CP15    0x000d          32      ;Process ID
cpacc           CP15    0x010f          32      ;Coprocessor Access
;
pmnc            CP14    0x0000          32      ;Performance Monitoring
ccnt            CP14    0x0001          32      ;Performance Monitoring
pmn0            CP14    0x0002          32      ;Performance Monitoring
pmn1            CP14    0x0003          32      ;Performance Monitoring
cclkcfg         CP14    0x0006          32      ;Clock Management
pwrmode         CP14    0x0007          32      ;Power Management
;
;       Expansion bus
;
exp_cs0         MM      0xc4000000
exp_cs1         MM      0xc4000004
exp_cs2         MM      0xc4000008
exp_cs3         MM      0xc400000c
exp_cfg0        MM      0xc4000020
exp_cfg1        MM      0xc4000024
;
;       DDR SDRAM Controller
;
sdir            MM      0xcc00e500
sdcr0           MM      0xcc00e504
sdcr1           MM      0xcc00e508
sdbr            MM      0xcc00e50c
sbr0            MM      0xcc00e510
sbr1            MM      0xcc00e514
eccr            MM      0xcc00e51c
elog0           MM      0xcc00e520
elog1           MM      0xcc00e524
ecar0           MM      0xcc00e528
ecar1           MM      0xcc00e52c
ectst           MM      0xcc00e530
mcisr           MM      0xcc00e534
mptcr           MM      0xcc00e53c
rfr             MM      0xcc00e548
;
sdpr0           MM      0xcc00e550
sdpr1           MM      0xcc00e554
sdpr2           MM      0xcc00e558
sdpr3           MM      0xcc00e55c
sdpr4           MM      0xcc00e560
sdpr5           MM      0xcc00e564
sdpr6           MM      0xcc00e568
sdpr7           MM      0xcc00e56c
;
;       PCI
;
np_ad           MM      0xc0000000
np_cbe          MM      0xc0000004
np_wdata        MM      0xc0000008
np_rdata        MM      0xc000000c
crp_ad_cbe      MM      0xc0000010
crp_wdata       MM      0xc0000014
crp_rdata       MM      0xc0000018
csr             MM      0xc000001c
isr             MM      0xc0000020
inten           MM      0xc0000024
dmactrl         MM      0xc0000028
ahbmembase      MM      0xc000002c
ahbiobase       MM      0xc0000030
pcimembase      MM      0xc0000034
ahbdoorbell     MM      0xc0000038
pcidoorbell     MM      0xc000003c
atpdma0_ahbaddr MM      0xc0000040
atpdma0_pciaddr MM      0xc0000044
atpdma0_length  MM      0xc0000048
atpdma1_ahbaddr MM      0xc000004c
atpdma1_pciaddr MM      0xc0000050
atpdma1_length  MM      0xc0000054
ptadma0_ahbaddr MM      0xc0000058
ptadma0_pciaddr MM      0xc000005c
ptadma0_length  MM      0xc0000060
ptadma1_ahbaddr MM      0xc0000064
ptadma1_pciaddr MM      0xc0000068
ptadma1_length  MM      0xc000006c
;
;       Queue Manager
;
qm_lowsts0      MM      0x60000400
qm_lowsts1      MM      0x60000404
qm_lowsts2      MM      0x60000408
qm_lowsts3      MM      0x6000040c
qm_undovrsts0   MM      0x60000410
qm_undovrsts1   MM      0x60000414
qm_nests        MM      0x60000418
qm_fsts         MM      0x6000041c
qm_irqflg0      MM      0x60000420
qm_irqflg1      MM      0x60000424
qm_irqflg2      MM      0x60000428
qm_irqflg3      MM      0x6000042c
qm_irqenb0      MM      0x60000430
qm_irqenb1      MM      0x60000434
qm_irqstsl      MM      0x60000438
qm_irqstsh      MM      0x6000043c
;
qm_cfg0         MM      0x60002000
qm_cfg1         MM      0x60002004
qm_cfg2         MM      0x60002008
qm_cfg3         MM      0x6000200c
qm_cfg4         MM      0x60002010
qm_cfg5         MM      0x60002014
qm_cfg6         MM      0x60002018
qm_cfg7         MM      0x6000201c
qm_cfg8         MM      0x60002020
qm_cfg9         MM      0x60002024
qm_cfg10        MM      0x60002028
qm_cfg11        MM      0x6000202c
qm_cfg12        MM      0x60002030
qm_cfg13        MM      0x60002034
qm_cfg14        MM      0x60002038
qm_cfg15        MM      0x6000203c
qm_cfg16        MM      0x60002040
qm_cfg17        MM      0x60002044
qm_cfg18        MM      0x60002048
qm_cfg19        MM      0x6000204c
qm_cfg20        MM      0x60002050
qm_cfg21        MM      0x60002054
qm_cfg22        MM      0x60002058
qm_cfg23        MM      0x6000205c
qm_cfg24        MM      0x60002060
qm_cfg25        MM      0x60002064
qm_cfg26        MM      0x60002068
qm_cfg27        MM      0x6000206c
qm_cfg28        MM      0x60002070
qm_cfg29        MM      0x60002074
qm_cfg30        MM      0x60002078
qm_cfg31        MM      0x6000207c
qm_cfg32        MM      0x60002080
qm_cfg33        MM      0x60002084
qm_cfg34        MM      0x60002088
qm_cfg35        MM      0x6000208c
qm_cfg36        MM      0x60002090
qm_cfg37        MM      0x60002094
qm_cfg38        MM      0x60002098
qm_cfg39        MM      0x6000209c
qm_cfg40        MM      0x600020a0
qm_cfg41        MM      0x600020a4
qm_cfg42        MM      0x600020a8
qm_cfg43        MM      0x600020ac
qm_cfg44        MM      0x600020b0
qm_cfg45        MM      0x600020b4
qm_cfg46        MM      0x600020b8
qm_cfg47        MM      0x600020bc
qm_cfg48        MM      0x600020c0
qm_cfg49        MM      0x600020c4
qm_cfg50        MM      0x600020c8
qm_cfg51        MM      0x600020cc
qm_cfg52        MM      0x600020d0
qm_cfg53        MM      0x600020d4
qm_cfg54        MM      0x600020d8
qm_cfg55        MM      0x600020dc
qm_cfg56        MM      0x600020e0
qm_cfg57        MM      0x600020e4
qm_cfg58        MM      0x600020e8
qm_cfg59        MM      0x600020ec
qm_cfg60        MM      0x600020f0
qm_cfg61        MM      0x600020f4
qm_cfg62        MM      0x600020f8
qm_cfg63        MM      0x600020fc
;
;       UART 1
;
uart_rbr1       MM      0xc8000000
uart_thr1       MM      0xc8000000
uart_ier1       MM      0xc8000004
uart_iir1       MM      0xc8000008
uart_fcr1       MM      0xc8000008
uart_lcr1       MM      0xc800000c
uart_mcr1       MM      0xc8000010
uart_lsr1       MM      0xc8000014
uart_msr1       MM      0xc8000018
uart_scr1       MM      0xc800001c
uart_isr1       MM      0xc8000020
;
;       UART 2
;
uart_rbr2       MM      0xc8001000
uart_thr2       MM      0xc8001000
uart_ier2       MM      0xc8001004
uart_iir2       MM      0xc8001008
uart_fcr2       MM      0xc8001008
uart_lcr2       MM      0xc800100c
uart_mcr2       MM      0xc8001010
uart_lsr2       MM      0xc8001014
uart_msr2       MM      0xc8001018
uart_scr2       MM      0xc800101c
uart_isr2       MM      0xc8001020
;
;       PMU
;
pmu_esr0        MM      0xc8002000
pmu_esr1        MM      0xc8002004
pmu_psr         MM      0xc8002010
pmu_pmr         MM      0xc8002014
pmu_pmsr        MM      0xc8002018
pmu_pec0        MM      0xc8002020
pmu_pec1        MM      0xc8002024
pmu_pec2        MM      0xc8002028
pmu_pec3        MM      0xc800202c
pmu_pec4        MM      0xc8002030
pmu_pec5        MM      0xc8002034
pmu_pec6        MM      0xc8002038
pmu_pec7        MM      0xc800203c
pmu_mpec0       MM      0xc8002040
pmu_mpec1       MM      0xc8002044
pmu_mpec2       MM      0xc8002048
pmu_mpec3       MM      0xc800204c
pmu_mpec4       MM      0xc8002050
pmu_mpec5       MM      0xc8002054
pmu_mpec6       MM      0xc8002058
pmu_mpec7       MM      0xc800205c
;
;       Interrupt controller
;
intc_st         MM      0xc8003000
intc_en         MM      0xc8003004
intc_sel        MM      0xc8003008
intc_irqst      MM      0xc800300c
intc_fiqst      MM      0xc8003010
intc_prty       MM      0xc8003014
intc_irqencst   MM      0xc8003018
intc_fiqencst   MM      0xc800301c
;
;       GPIO
;
gpio_gpoutr     MM      0xc8004000
gpio_gpoer      MM      0xc8004004
gpio_gpinr      MM      0xc8004008
gpio_gpisr      MM      0xc800400c
gpio_gpit1r     MM      0xc8004010
gpio_gpit2r     MM      0xc8004014
gpio_gpclk      MM      0xc8004018
;
;       Timer
;
tmr_ts          MM      0xc8005000
tmr_tim0        MM      0xc8005004
tmr_tim0rl      MM      0xc8005008
tmr_tim1        MM      0xc800500c
tmr_tim1rl      MM      0xc8005010
tmr_wdog        MM      0xc8005014
tmr_wdogenab    MM      0xc8005018
tmr_wdogkey     MM      0xc800501c
tmt_sts         MM      0xc8005020
;

