;Register definition for IQ80321
;===============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	CP15	CP15 register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;
; CP15 Registers Numbers for xScale:
;
;       +-----+-+-------+-----+-+-------+
;       |opc_2|0|  CRm  |opc_1|0|  nbr  |
;       +-----+-+-------+-----+-+-------+
;
; The 16bit register number is used to build the appropriate MCR/MRC instruction.
;
;
;name		type	addr		size
;-------------------------------------------
;
id		CP15    0x0000          32      ;ID code
cache   	CP15    0x2000          32      ;Cache type
ctr             CP15    0x0001          32      ;Control
aux     	CP15    0x2001          32      ;Auxiliary Control
ttb             CP15    0x0002          32      ;Translation Table Base
dac             CP15    0x0003          32      ;Domain Access Control
fsr     	CP15    0x0005          32      ;Fault Status
far     	CP15    0x0006          32      ;Fault Address
pid        	CP15    0x000d          32      ;Process ID
cpacc      	CP15    0x010f          32      ;Coprocessor Access
;
bear        	CP7     0x0000          32      ;BIU Error Address Register
biusr       	CP7     0x0004          32      ;BIU Status Register
;
intctl      	CP6     0x0000          32      ;Interrupt Control Register
intstr      	CP6     0x0004          32      ;Interrupt Steering Register
iintsrc     	CP6     0x0008          32      ;IRQ Interrupt Source Register
fintsrc     	CP6     0x0009          32      ;FIQ Interrupt Source Register
;
tmr0        	CP6     0x0100          32      ;Timer Mode Register 0
tcr0        	CP6     0x0102          32      ;Timer Count Register 0
trr0        	CP6     0x0104          32      ;Timer Reload Register 0
tmr1        	CP6     0x0101          32      ;Timer Mode Register 1
tcr1        	CP6     0x0103          32      ;Timer Count Register 1
trr1        	CP6     0x0105          32      ;Timer Reload Register 1
tisr        	CP6     0x0106          32      ;Timer Interrupt Status Register
wdtcr       	CP6     0x0107          32      ;Watch Dog Timer Control Register
;
;
;       Memory controller
;
sdir            MM      0xffffe500
sdcr            MM      0xffffe504
sdbr            MM      0xffffe508
sbr0            MM      0xffffe50c
sbr1            MM      0xffffe510
;
eccr            MM      0xffffe534
elog0           MM      0xffffe538
elog1           MM      0xffffe53c
ecar0           MM      0xffffe540
ecar1           MM      0xffffe544
ectst           MM      0xffffe548
mcisr           MM      0xffffe54c
rfr             MM      0xffffe550
;
dbudsr          MM      0xffffe554
dbddsr          MM      0xffffe558
cudsr           MM      0xffffe55c
cddsr           MM      0xffffe560
ceudsr          MM      0xffffe564
ceddsr          MM      0xffffe568
csudsr          MM      0xffffe56c
csddsr          MM      0xffffe570
reudsr          MM      0xffffe574
reddsr          MM      0xffffe578
abudsr          MM      0xffffe57c
abddsr          MM      0xffffe580
;
;       Peripheral Bus Interface Unit
;
pbcr            MM      0xffffe680
pbisr           MM      0xffffe684
pbbar0          MM      0xffffe688
pblr0           MM      0xffffe68c
pbbar1          MM      0xffffe690
pblr1           MM      0xffffe694
pbbar2          MM      0xffffe698
pblr2           MM      0xffffe69c
pbbar3          MM      0xffffe6a0
pblr3           MM      0xffffe6a4
pbbar4          MM      0xffffe6a8
pblr4           MM      0xffffe6ac
pbbar5          MM      0xffffe6b0
pblr5           MM      0xffffe6b4
pbdscr          MM      0xffffe6b8
pmbr0           MM      0xffffe6c0
pmbr1           MM      0xffffe6e0
pmbr2           MM      0xffffe6e4
;
