; bdiGDB configuration file for two daisy chained Cogent CSB226 Boards
; --------------------------------------------------------------------
;
;         +------------+    +------------+
;  TDI ---| old CSB226 |----| new CSB226 |---- TDO
;         +------------+    +------------+
;            core #0           core #1
;
[INIT]
;core #0 is old CSB226
;=====================
#0 WCP15   0x010F      0x00002001  ;Enable CP0 and CP13 access
;
; setup memory controller
;
#0 WM32    0x48000008  0x2ef15af8  ;MSC0
#0 WM32    0x4800000C  0x00003ff4  ;MSC1
#0 WM32    0x48000004  0x03ca4fff  ;MDREF  : chip default
#0 WM32    0x48000004  0x03ca4030  ;MDREF  : REF Rate = (64MS/4096 Rows)/32 = 48
#0 WM32    0x48000004  0x03cf6030  ;MDREF  : Set K0RUN, K1RUN and K2RUN
#0 WM32    0x48000004  0x038f6030  ;MDREF  : Clear Self Refresh
#0 WM32    0x48000004  0x038ff030  ;MDREF  : Set E0PIN and E1PIN
#0 WM32    0x48000000  0x09a809a8  ;MDCNFG : don't enable just yet
#0 DELAY   20
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0xA0000000  0xA0000000  ;access SDRAM
#0 WM32    0x48000000  0x09a909a9  ;MDCNFG : now enable SDRAM
#0 WM32    0x48000040  0x00220022  ;MDMRS  : and do an MRS
;
;core #1 is new CSB226
;=====================
#1 WCP15   0x010F      0x00002001  ;Enable CP0 and CP13 access
;
; setup memory controller
#1 WM32    0x48000008  0x2ef025d0  ;MSC0
#1 WM32    0x4800000C  0x3f643f64  ;MSC1
#1 WM32    0x48000010  0x00003f60  ;MSC2
#1 WM32    0x48000004  0x03ca4fff  ;MDREF  : chip default
#1 WM32    0x48000004  0x03ca4030  ;MDREF  : REF Rate = (64MS/4096 Rows)/32 = 48
#1 WM32    0x48000004  0x03cf6030  ;MDREF  : Set Clock Run Bits
#1 WM32    0x48000004  0x038f6030  ;MDREF  : Clear Self Refresh
#1 WM32    0x48000004  0x038ff030  ;MDREF  : Set E0PIN and E1PIN
#1 WM32    0x48000000  0x09a809a8  ;MDCNFG : don't enable just yet
#1 DELAY   20
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0xA0000000  0xA0000000  ;access SDRAM
#1 WM32    0x48000000  0x09a909a9  ;MDCNFG : now enable SDRAM
#1 WM32    0x48000040  0x00220022  ;MDMRS  : and do a MRS
;

[TARGET]
JTAGCLOCK       3               ;use 8 MHz JTAG clock
POWERUP         2000            ;start delay after power-up detected in ms
;WAKEUP          1000            ;give reset time to complete

#0 CPUTYPE      PXA250          ;the target CPU type
#0 SCANPRED     0 0             ;JTAG devices connected before this core
#0 SCANSUCC     1 5             ;JTAG devices connected after this core
#0 DBGHANDLER   0xFFFF0800      ;debug handler base address
#0 ENDIAN       LITTLE          ;memory model (LITTLE | BIG)
#0 BREAKMODE    SOFT            ;SOFT or HARD
#0 VECTOR       CATCH 0xDE      ;trap all vectors
;#0 VTABLO       0xe59ff018      ;Use fixed vectors "ldr pc, [pc, #18]"
#0 VTABHI       0xffffffff      ;Do not update relocated vector table

#1 CPUTYPE      PXA250          ;the target CPU type
#1 SCANPRED     1 5             ;JTAG devices connected before this core
#1 SCANSUCC     0 0             ;JTAG devices connected after this core
#1 DBGHANDLER   0xFFFF0800      ;debug handler base address
#1 ENDIAN       LITTLE          ;memory model (LITTLE | BIG)
#1 BREAKMODE    SOFT            ;SOFT or HARD
#1 VECTOR       CATCH 0xDE      ;trap all vectors
#1 VTABLO       0xEA000012      ;Use fixed vectors "b xxx"
#1 VTABHI       0xffffffff      ;Do not update relocated vector table


[HOST]
#0 IP           151.120.25.119
#0 FILE         E:\cygwin\home\bdidemo\xscale\vxworks
#0 FORMAT       BIN 0xA0020000
#0 LOAD         MANUAL          ;load code code MANUAL or AUTO after reset

#1 IP           151.120.25.119
#1 FILE         E:\cygwin\home\bdidemo\xscale\vxworks
#1 FORMAT       BIN 0xA0020000
#1 LOAD         MANUAL          ;load code code MANUAL or AUTO after reset

[FLASH]
#0 WORKSPACE    0xA0000000      ;workspace in target RAM for fast programming algorithm
#0 CHIPTYPE     STRATAX16       ;Flash type
#0 CHIPSIZE     0x1000000       ;The size of one flash chip in bytes
#0 BUSWIDTH     16              ;The width of the flash memory bus in bits (8 | 16 | 32)
#0 FILE         E:\cygwin\home\bdidemo\xscale\regPXA250.def
#0 FORMAT       BIN 0x00180000
#0 ERASE        0x00180000      ;erase sector 12

#1 WORKSPACE    0xA0000000      ;workspace in target RAM for fast programming algorithm
#1 CHIPTYPE     STRATAX16       ;Flash type
#1 CHIPSIZE     0x1000000       ;The size of one flash chip in bytes
#1 BUSWIDTH     32              ;The width of the flash memory bus in bits (8 | 16 | 32)
#1 FILE         E:\cygwin\home\bdidemo\xscale\regPXA250.def
#1 FORMAT       BIN 0x00100000
#1 ERASE        0x00100000      ;erase sector 4

[REGS]
#0 FILE         E:\cygwin\home\bdidemo\xscale\regPXA250.def
#1 FILE         E:\cygwin\home\bdidemo\xscale\regPXA250.def