; bdiGDB configuration file for IQ80331 board
; -------------------------------------------
; The DDR setup was read back after RedBoot has setup the board.
; The used DDR parameters may not mach your configuration.
; Let RedBoot setup your board, for example with "reset run".
; Then read back the relevant SDRAM registers and update the
; init list entires.
;
; SDRAM is mapped to 0x00000000
; Flash is mapped to 0xC0000000
;
;
[INIT]
WCP15   0x2001      0x00000001  ;Disable Write Buffer Coalescing
WCP15   0x010F      0x000020C1  ;Enable CP0, CP6, CP7 and CP13 access
;
; Setup PBI Bus
;
WM32    0xFFFFE688  0xc00003dc  ;PBBAR0: PCE0 @ 0xC0000000 (Flash)
WM32    0xFFFFE68C  0xff800000  ;PBLR0 : 8MB
WM32    0xFFFFE690  0xce8003dc  ;PBBAR1: PCE1 @ 0xCE800000
WM32    0xFFFFE694  0xfff00000  ;PBLR1 : 1MB
;
; Init DDR SDRAM
; Setup for Micron 256 DIMMs
WM32    0xFFFFE50C  0x00000000	;Set SDBR
WM32    0xFFFFE510  0x00000008	;Set SBRO
WM32    0xFFFFE514  0x00000008	;Set SBR1
WM32    0xFFFFE504  0x62220105	;Set SDCR0
WM32    0xFFFFE508  0x1470b095	;Set SDCR1
WM32    0xFFFFE548  0x00000000	;Set RFR-Refresh Rate to zero
WM32    0xFFFFE500  0x00000003	;SDIR- Issue a NOP to DIMM
;
; Setup DIMM parameters
WM32    0xFFFFE500  0x00000002	;SDIR- PreCharge All
WM32    0xFFFFE500  0x00000004	;SDIR- Extend Mode Register (Dll Enable)
WM32    0xFFFFE500  0x00000001	;SDIR- Mode Register Set (Reset DLL, w/CAS & Burst  4)
WM32    0xFFFFE500  0x00000002	;SDIR- PreCharge All
WM32    0xFFFFE500  0x00000006	;SDIR- Auto Refresh
WM32    0xFFFFE500  0x00000006	;SDIR- Auto Refresh
DELAY   10                      ;Insert delay here
WM32    0xFFFFE500  0x00000000	;SDIR- Mode Register Set (Don't reset DLL)
WM32    0xFFFFE500  0x0000000f	;SDIR- Normal Operation (not in C-Spec)
WM32    0xFFFFE548  0x000007fe	;Set RFR-Refresh Rate
DELAY   10                      ;Insert delay here
WM32    0xFFFFE530  0x00000000	;ECTST- Clear ECC bit test register
;WM32    0xFFFFE51C  0x00000000	;ECCR - Disable ECC and ECC error reporting
WM32    0xFFFFE51C  0x0000000f	;ECCR - Enable ECC and ECC error reporting
FILL    0x00000000  0x10000000  ;fill DDR SDRAM if ECC enabled
;
; DDR-II Tuning
;WM32 0xFFFFF550  0x00000002	;RCVDLY- set Receive Enable Delay
;
WM8     0xCE840000  0x7C        ;LED shows "UP"
WM8     0xCE850000  0xE6
;

[TARGET]
CPUTYPE         IOP331          ;the target CPU type
SCANPRED        0 0             ;there is no TAP before the XScale core
SCANSUCC        1 7             ;there is a second TAP (TLU)
JTAGCLOCK       1               ;use 16 MHz JTAG clock
DBGHANDLER      0xFFFF0800      ;debug handler base address
ENDIAN          LITTLE          ;memory model (LITTLE | BIG)
BREAKMODE       SOFT            ;SOFT or HARD
;VECTOR          CATCH 0xDE      ;trap all vectors
VTABLO          0xe59ff018      ;Use fixed vetors "ldr pc, [pc, #18]"
VTABHI          0xffffffff      ;Do not update relocated vector table

[HOST]
IP              151.120.25.119
FILE            E:\cygwin\home\bdidemo\xscale\iop331\redboot.bin
FORMAT          BIN 0x00010000
LOAD            MANUAL          ;load code code MANUAL or AUTO after reset

[FLASH]
WORKSPACE       0x00001000      ;workspace in SDRAM for fast programming algorithm
CHIPTYPE        STRATAX8        ;Flash type
CHIPSIZE        0x800000        ;The size of one flash chip in bytes
BUSWIDTH        8               ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE            E:\cygwin\home\bdidemo\xscale\iop331\redboot.bin
FORMAT          BIN 0xC0080000
ERASE           0xC0080000      ;erase sector 4
ERASE           0xC00A0000      ;erase sector 5
ERASE           0xC00C0000      ;erase sector 6
ERASE           0xC00E0000      ;erase sector 7
ERASE           0xC0100000      ;erase sector 8
ERASE           0xC0120000      ;erase sector 9
ERASE           0xC0140000      ;erase sector 10
ERASE           0xC0160000      ;erase sector 11
ERASE           0xC0180000      ;erase sector 12
ERASE           0xC01A0000      ;erase sector 13
ERASE           0xC01C0000      ;erase sector 14
ERASE           0xC01E0000      ;erase sector 15

[REGS]
FILE    $reg80331.def