;bdiGDB configuration file for T1040-QDS ;--------------------------------------- ; [INIT] ; ; Setup TLB1 for core#0 ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000700_0xff00000a 0x10000000_0xff00003f ;1/0: ff000000->0_ff000000 16MB -I-G- RWXRWX WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX WTLB 0x80000400_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 256kB ----- RWXRWX ; ; Initialize LAWBAR's WREG lawbarh0 0x00000000 ;Flash @0_e0000000 WREG lawbarl0 0xe0000000 WREG lawar0 0x81f0001b ;IFC 256MB ; WREG lawbarh1 0x00000000 ;CPC/SRAM @0_80000000 WREG lawbarl1 0x80000000 WREG lawar1 0x81000011 ;DDR/CPC 256kB ; WREG lawbarh15 0x00000000 ;SDRAM @0_00000000 WREG lawbarl15 0x00000000 WREG lawar15 0x8100001e ;DDR/CPC 2GB ; ; Integrated Flash Controller (IFC) WREG ifc_cspr0_ext 0x00000000 ;Map 8MByte of NOR Flash to 0xff800000 WREG ifc_cspr0 0xff800101 WREG ifc_amask0 0xff800000 ; ;WREG ifc_cspr0_ext 0x00000000 ;Map 128 MByte of NOR Flash to 0xe8000000 ;WREG ifc_cspr0 0xe8000101 ;WREG ifc_amask0 0xf8000000 ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WREG cpc_srcr1 0x00000000 ;high address WREG cpc_srcr0 0x80000007 ;all 8 ways as SRAM WREG cpc_csr0 0x80000000 ;CPC enable WREG cpc_hdbcr0 0x08000000 ;Speculation disable ; ; Release cores for booting WREG brr 0x0000000f ;BRR: release cores ; ; Setup TLB1 for core #1,#2,#3 ; MAS1 MAS2 MAS0/MAS7 MAS3 #1 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #1 WTLB 0x80000400_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 256kB ----- RWXRWX #2 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #2 WTLB 0x80000400_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 256kB ----- RWXRWX #3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #3 WTLB 0x80000400_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 256kB ----- RWXRWX ; ; write DNH instruction to default vector WM32 0x80000000 0x4c00018c ;catch default vector ; ; write a loop to CPC1/SRAM (for test only) WM32 0x80000100 0x3c6005f6 ;lis r3,1526 (100'000'000) WM32 0x80000104 0x38800000 ;li r4,0 WM32 0x80000108 0x38a00000 ;li r5,0 WM32 0x8000010c 0x38a50008 ;addi r5,r5,8 WM32 0x80000110 0x38840008 ;addi r4,r4,8 WM32 0x80000114 0x3463ffff ;addic. r3,r3,-1 WM32 0x80000118 0x4082fff4 ;bne bc WM32 0x8000011c 0x4bffffe4 ;b b0 WM32 0x80000120 0x60000000 ;nop WM32 0x80000124 0x60000000 ;nop ; ; set PC to start of loop #0 WREG pc 0x80000100 #1 WREG pc 0x80000100 #2 WREG pc 0x80000100 #3 WREG pc 0x80000100 ; ; set default vector #0 WREG ivpr 0x80000000 #1 WREG ivpr 0x80000000 #2 WREG ivpr 0x80000000 #3 WREG ivpr 0x80000000 ; ;========================================================================================= ; define the valid memory map (GDB may access invalid memory) #0 MMAP 0x80000000 0x8003ffff ;CPC1/SRAM 256kByte #0 MMAP 0xfe000000 0xfeffffff ;Memory map for Internal Register #0 MMAP 0xff000000 0xffffffff ;Boot space ; #1 MMAP 0x80000000 0x8003ffff ;CPC1/SRAM 256kByte #1 MMAP 0xfe000000 0xfeffffff ;Memory map for Internal Register #1 MMAP 0xff000000 0xffffffff ;Boot space ; #2 MMAP 0x80000000 0x8003ffff ;CPC1/SRAM 256kByte #2 MMAP 0xfe000000 0xfeffffff ;Memory map for Internal Register #2 MMAP 0xff000000 0xffffffff ;Boot space ; #3 MMAP 0x80000000 0x8003ffff ;CPC1/SRAM 256kByte #3 MMAP 0xfe000000 0xfeffffff ;Memory map for Internal Register #3 MMAP 0xff000000 0xffffffff ;Boot space ; ;========================================================================================= ; setup device trigger, debug halt always all cores WREG cgcr0 0x0000000f ;CGCR0: Core Group 0 (0,1,2,3) WREG cgcr1 0x0000000f ;CGCR1: Core Group 1 (0,1,2,3) WREG cgcr2 0x0000000f ;CGCR2: Core Group 2 (0,1,2,3) WREG csttacr0 0x00000801 ;CSTTACR0: trigger if a core from group 1 enter debug halt ; WREG cgacrd4 0x00000022 ;CGACRD4 : if device event, halt cores in group 2 ; ;WREG epsmcr13 0x0C000000 ;EPSMCR13[ISEL0] = 12 (RCPM Concerntrator 0 Event) ;WREG epecr13 0x80000000 ;EPECR13[IC0] = 2 (Input 0 is sufficient) ;WREG cgacre13 0x00000022 ;CGACRE13: if EPU event, halt cores in group 2 [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 16000000 ;16 MHz JTAG clock RESET HARD 1000 ;assert reset for 1 seconds WAKEUP 500 ;give reset time to complete ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE T1040 2 0 !!!! ;======================================================== ; ; Core#0 parameters (active core after reset) #0 CPUTYPE T1040 0 0 ;Core0 / SOC0 #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint #0 MEMACCESS CORE #0 CGROUP 0x0f ;GDB continue core group (resume) ; ; CoreID#1 parameters #1 CPUTYPE T1040 1 0 ;Core#1 / SOC#0 #1 STARTUP HALT ;halt at the reset vector #1 BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint #1 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint #1 MEMACCESS CORE #1 CGROUP 0x02 ;GDB continue core group (prepare) ; ; CoreID#1 parameters #2 CPUTYPE T1040 2 0 ;Core#2 / SOC#0 #2 STARTUP HALT ;halt at the reset vector #2 BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint #2 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint #2 MEMACCESS CORE #2 CGROUP 0x04 ;GDB continue core group (prepare) ; ; CoreID#1 parameters #3 CPUTYPE T1040 3 0 ;Core#3 / SOC#0 #3 STARTUP HALT ;halt at the reset vector #3 BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint #3 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint #3 MEMACCESS CORE #3 CGROUP 0x08 ;GDB continue core group (prepare) ; [HOST] FILE E:\temp\dump256k.bin FORMAT BIN 0x80000000 ; #0 PROMPT T1040#0> #1 PROMPT T1040#1> #2 PROMPT T1040#2> #3 PROMPT T1040#3> [FLASH] ;flash is S29GL01GS WORKSPACE 0x80001000 ;workspace in CPC1/SRAM CHIPTYPE MIRRORX16 ;Flash type is S29GL01GS CHIPSIZE 0x00800000 ;visible size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits FILE E:\temp\dump256k.bin FORMAT BIN 0xffe00000 ERASE 0xffe00000 0x20000 4 ;FORMAT BIN 0xefe00000 ;ERASE 0xefe00000 0x20000 4 [REGS] FILE $regT1040.def