;bdiGDB configuration file for P4080-DS ;-------------------------------------- ; ; The values used to configure the memory controller ; are the ones U-boot uses to setup my system. ; Your system may need different ones !!! ; ; [INIT] ; ; Setup TLB1 ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX WTLB 0x80000500_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 1MB ----- RWXRWX ; ;========================================================================================= ; Setup TLB0 (for test purpose only) ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000100_0xc0000000 0x00000000_0x0000003f ;WAY0: c0000000->0_00000000 4KB ----- RWXRWX WTLB 0x80000100_0xc0001000 0x00000000_0x0000103f ;WAY0: c0001000->0_00001000 4KB ----- RWXRWX WTLB 0x80000100_0xc0002000 0x00000000_0x0000203f ;WAY0: c0002000->0_00002000 4KB ----- RWXRWX WTLB 0x80000100_0xc0003000 0x00000000_0x0000303f ;WAY0: c0003000->0_00003000 4KB ----- RWXRWX ;========================================================================================= ; ;========================================================================================= ; Execute (IJAM) some instruction (for test purpose only) EXEC 0_0x3c60aba4 ;load GPR 3 via lui instruction EXEC 1_0x80c00000 0xdeadbeef ;load GPR 6 via lwz instruction with 1 parameters EXEC 2_0xc8c00000 0x123456789abcdef0 ;load FPR 6 via ldf instruction with 2 parameters ;========================================================================================= ; ; Initialize LAWBAR's WM32 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 WM32 0xfe000c04 0xe0000000 WM32 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB ; WM32 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 WM32 0xfe000c14 0x80000000 WM32 0xfe000c18 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB ; WM32 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 WM32 0xfe000df4 0x00000000 WM32 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WM32 0xfe010104 0x8000000b ;CPC1_SRCR0: all 32 ways as SRAM WM32 0xfe010000 0x80000000 ;CPC1_CSR0 : CPC enable WM32 0xfe010f00 0x08000000 ;CPC 4 Errata ; ; Local Bus Controller WM32 0xfe124004 0xf8000ff7 ;OR0: WM32 0xfe124000 0xe8001001 ;BR0: WM32 0xfe12400c 0xf8000ff7 ;OR1: WM32 0xfe124008 0xe0001001 ;BR1: ; ; Setup DDR controller 1 WM32 0xfe008000 0x0000003f ;CS0_BNDS WM32 0xfe008008 0x0040007f ;CS1_BNDS WM32 0xfe008010 0x00000000 ;CS2_BNDS WM32 0xfe008018 0x00000000 ;CS3_BNDS WM32 0xfe008080 0x80014202 ;CS0_CONFIG WM32 0xfe008084 0x80014202 ;CS1_CONFIG WM32 0xfe008088 0x00000000 ;CS2_CONFIG WM32 0xfe00808C 0x00000000 ;CS3_CONFIG WM32 0xfe0080C0 0x00000000 ;CS0_CONFIG_2 WM32 0xfe0080C4 0x00000000 ;CS1_CONFIG_2 WM32 0xfe0080C8 0x00000000 ;CS2_CONFIG_2 WM32 0xfe0080CC 0x00000000 ;CS3_CONFIG_2 WM32 0xfe008100 0x01031000 ;TIMING_CFG_3 WM32 0xfe008104 0x55440804 ;TIMING_CFG_0 WM32 0xfe008108 0x74713a66 ;TIMING_CFG_1 WM32 0xfe00810C 0x0fb8911b ;TIMING_CFG_2 WM32 0xfe008110 0x47048000 ;DDR_CFG WM32 0xfe008114 0x24401011 ;DDR_CFG_2 WM32 0xfe008118 0x00421850 ;DDR_MODE WM32 0xfe00811C 0x00100000 ;DDR_MODE_2 WM32 0xfe008124 0x10400100 ;DDR_INTERVAL WM32 0xfe008128 0xdeadbeef ;DDR_DATA_INIT WM32 0xfe008130 0x03000000 ;DDR_CLK_CNTL WM32 0xfe008148 0x00000000 ;DDR_INIT_ADDR WM32 0xfe00814C 0x00000000 ;DDR_INIT_EXT_ADDR WM32 0xfe008160 0x00220001 ;TIMING_CFG_4 WM32 0xfe008164 0x03401500 ;TIMING_CFG_5 WM32 0xfe008170 0x89080600 ;DDR_ZQ_CNTL WM32 0xfe008174 0x8655a608 ;DDR_WRLVL_CNTL WM32 0xfe008B28 0x00000000 ;DDRCDR_1 WM32 0xfe008B2C 0x00000000 ;DDRCDR_2 DELAY 100 WM32 0xfe008110 0xc7048000 ;DDR_CFG DELAY 1000 ; ; Release cores for booting WM32 0xfe0E00E4 0x00000007 ;BRR: release core 0, 1 and 2 ; ; Setup TLB1 for core #1 ; MAS1 MAS2 MAS0/MAS7 MAS3 #1 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #1 WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX #1 WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX #1 WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX #1 WTLB 0x80000500_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 1MB ----- RWXRWX ; ; Setup TLB1 for core #2 ; MAS1 MAS2 MAS0/MAS7 MAS3 #2 WTLB 0x80000900_0xf000000a 0x10000000_0xe000003f ;1/2: f0000000->0_e0000000 256MB -I-G- RWXRWX ; ; ; write DNH instruction to default vector WM32 0x00000000 0x4c00018c ;catch default vector ; ; limit memory access size ;TSZ4 0xe0000000 0xefffffff ;flash range ; [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 1 ;use 16 MHz JTAG clock WAKEUP 1000 ;give reset time to complete ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE P4080 5 0 !!!! ;======================================================== ; ; CoreID#0 parameters (active vCPU after reset) #0 CPUTYPE P4080 0 0 ;Core0 / SOC0 #0 EDBCR0 EDM DNH EFT ;set run parameters #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint ; ; RCW Override for SOC#0 assigned to CoreID#0 ; don't override PLL configuration in RCW[0]-RCW[3] ;#0 RCWSRC 0x18 ;Hard-Coded RCW 1_1000 ;#0 RCWOVR 0 0x4a540000 ; 0: don't override !!! ;#0 RCWOVR 1 0x00000000 ; 32: don't override !!! ;#0 RCWOVR 2 0x18181818 ; 64: don't override !!! ;#0 RCWOVR 3 0x00008888 ; 96: don't override !!! ;#0 RCWOVR 4 0x90404000 ;128: ;#0 RCWOVR 5 0x00002000 ;160: ;#0 RCWOVR 6 0xfe800000 ;192: ;#0 RCWOVR 7 0x01000000 ;224: ;#0 RCWOVR 8 0x00000000 ;256: ;#0 RCWOVR 9 0x00000000 ;288: ;#0 RCWOVR 10 0x00000000 ;320: ;#0 RCWOVR 11 0x00830000 ;352: ;#0 RCWOVR 12 0x00000000 ;384: ;#0 RCWOVR 13 0x00000000 ;416: ;#0 RCWOVR 14 0x00000000 ;448: ;#0 RCWOVR 15 0x00000000 ;480: ; ; ; CoreID#1 parameters #1 CPUTYPE P4080 1 0 ;Core1 / SOC0 #1 EDBCR0 EDM DNH EFT ;set run parameters #1 STARTUP HALT ;halt at the reset vector ; ; CoreID#2 parameters #2 CPUTYPE P4080 2 0 ;Core2 / SOC0 #2 STARTUP HALT ;halt at the reset vector ; [HOST] IP 151.120.25.112 FILE E:\temp\dump1024k.bin FORMAT BIN 0x10000 ; #0 PROMPT P4080#0> #1 PROMPT P4080#1> #2 PROMPT P4080#2> ; #0 DEBUGPORT 4080 #1 DEBUGPORT 4081 #2 DEBUGPORT 4082 ; [FLASH] ;WORKSPACE 0x00001000 ;workspace in SDRAM WORKSPACE 0x80001000 ;workspace in CPC1/SRAM ; only to test execution of target code ;CHIPTYPE AM29BX16 ;Flash type ;CHIPSIZE 0x00200000 ;The size of one flash chip in bytes ;BUSWIDTH 16 ;The width of the flash memory bus in bits ;FILE E:\temp\dump1024k.bin ;FORMAT BIN 0x00300000 ;flash is S29GL01GP CHIPTYPE MIRRORX16 ;Flash type is S29GL01GP CHIPSIZE 0x08000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits FILE E:\temp\dump512k.bin FORMAT BIN 0xed800000 ERASE 0xed800000 0x20000 4 [REGS] FILE $regP4080.def