;bdiGDB configuration file for P3041-DS ;-------------------------------------- ; ; The values used to configure the memory controller ; are the ones U-boot uses to setup my system. ; Your system may need different ones !!! ; ; [INIT] ; ; Setup TLB1 ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX WTLB 0x80000500_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 1MB ----- RWXRWX ; ;========================================================================================= ; Setup TLB0 (for test purpose only) ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000100_0xc0000000 0x00000000_0x0000003f ;WAY0: c0000000->0_00000000 4KB ----- RWXRWX WTLB 0x80000100_0xc0001000 0x00000000_0x0000103f ;WAY0: c0001000->0_00001000 4KB ----- RWXRWX WTLB 0x80000100_0xc0002000 0x00000000_0x0000203f ;WAY0: c0002000->0_00002000 4KB ----- RWXRWX WTLB 0x80000100_0xc0003000 0x00000000_0x0000303f ;WAY0: c0003000->0_00003000 4KB ----- RWXRWX ;========================================================================================= ; ; Initialize LAWBAR's WM32 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 WM32 0xfe000c04 0xe0000000 WM32 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB ; WM32 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 WM32 0xfe000c14 0x80000000 WM32 0xfe000c18 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB ; WM32 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 WM32 0xfe000df4 0x00000000 WM32 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WM32 0xfe010100 0x00000000 ;CPC1_SRCR1 : high address WM32 0xfe010104 0x8000000b ;CPC1_SRCR0 : all 32 ways as SRAM WM32 0xfe010000 0x80000000 ;CPC1_CSR0 : CPC enable WM32 0xfe010f00 0x08000000 ;CPC1_HDBCR0: Speculation disable ; ; Local Bus Controller WM32 0xfe124004 0xf8000ff7 ;OR0: WM32 0xfe124000 0xe8001001 ;BR0: WM32 0xfe12400c 0xf8000ff7 ;OR1: WM32 0xfe124008 0xe0001001 ;BR1: ; ; Setup DDR controller 1 WM32 0xfe008000 0x0000007f ;CS0_BNDS WM32 0xfe008008 0x00000000 ;CS1_BNDS WM32 0xfe008010 0x00000000 ;CS2_BNDS WM32 0xfe008018 0x00000000 ;CS3_BNDS WM32 0xfe008080 0x80044202 ;CS0_CONFIG WM32 0xfe008084 0x00000000 ;CS1_CONFIG WM32 0xfe008088 0x00000000 ;CS2_CONFIG WM32 0xfe00808C 0x00000000 ;CS3_CONFIG WM32 0xfe0080C0 0x00000000 ;CS0_CONFIG_2 WM32 0xfe0080C4 0x00000000 ;CS1_CONFIG_2 WM32 0xfe0080C8 0x00000000 ;CS2_CONFIG_2 WM32 0xfe0080CC 0x00000000 ;CS3_CONFIG_2 WM32 0xfe008100 0x00020000 ;TIMING_CFG_3 WM32 0xfe008104 0x40110104 ;TIMING_CFG_0 WM32 0xfe008108 0x6f6b4644 ;TIMING_CFG_1 WM32 0xfe00810C 0x0fa888cc ;TIMING_CFG_2 WM32 0xfe008110 0x47044000 ;DDR_CFG WM32 0xfe008114 0x24401111 ;DDR_CFG_2 WM32 0xfe008118 0x00441420 ;DDR_MODE WM32 0xfe00811C 0x00000000 ;DDR_MODE_2 WM32 0xfe008124 0x0c300100 ;DDR_INTERVAL WM32 0xfe008128 0xdeadbeef ;DDR_DATA_INIT WM32 0xfe008130 0x02800000 ;DDR_CLK_CNTL WM32 0xfe008148 0x00000000 ;DDR_INIT_ADDR WM32 0xfe00814C 0x00000000 ;DDR_INIT_EXT_ADDR WM32 0xfe008160 0x00000001 ;TIMING_CFG_4 WM32 0xfe008164 0x02401400 ;TIMING_CFG_5 WM32 0xfe008170 0x89080600 ;DDR_ZQ_CNTL WM32 0xfe008174 0x8675f606 ;DDR_WRLVL_CNTL WM32 0xfe008B28 0x80000000 ;DDRCDR_1 WM32 0xfe008B2C 0x00000000 ;DDRCDR_2 DELAY 100 WM32 0xfe008110 0xc7044000 ;DDR_CFG DELAY 1000 ; ; write DNH instruction to default vector WM32 0x00000000 0x4c00018c ;catch default vector WM32 0x00000004 0x38800000 ;li r4,0 WM32 0x00000008 0x60000000 ;NOP WM32 0x0000000c 0x60000000 ;NOP WM32 0x00000010 0x38840001 ;addi r4,r4,1 WM32 0x00000014 0x60000000 ;NOP WM32 0x00000018 0x60000000 ;NOP WM32 0x0000001c 0x4bfffff0 ;b ; ; Release cores WM32 0xfe0e00e4 0x0000000f ;BRR: release core 0, 1, 2 and 3 ; ; Setup TLB1 for core #1,2,3 ; MAS1 MAS2 MAS0/MAS7 MAS3 #1 WTLB 0x80000a00_0x00000000 0x10010000_0x0000003f ;1/1: 00000000->0_00000000 1GB ----- RWXRWX #2 WTLB 0x80000a00_0x00000000 0x10010000_0x0000003f ;1/1: 00000000->0_00000000 1GB ----- RWXRWX #3 WTLB 0x80000a00_0x00000000 0x10010000_0x0000003f ;1/1: 00000000->0_00000000 1GB ----- RWXRWX ; ; let PC point to endless loop #0 WREG pc 0x00000004 ;PC = 0x00000004 #1 WREG pc 0x00000004 ;PC = 0x00000004 #2 WREG pc 0x00000004 ;PC = 0x00000004 #3 WREG pc 0x00000004 ;PC = 0x00000004 [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 1 ;use 16 MHz JTAG clock RESET HARD 500 ;assert reset for 0.5 seconds WAKEUP 200 ;give reset time to complete ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE P4080 5 0 !!!! ;======================================================== ; ; CoreID#0 parameters (active vCPU after reset) #0 CPUTYPE P3041 0 0 ;Core#0 / SOC#0 #0 EDBCR0 EDM DNH EFT ;set run parameters #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint ; ; CoreID#1 parameters #1 CPUTYPE P3041 1 0 ;Core#1 / SOC#0 #1 EDBCR0 EDM DNH EFT ;set run parameters #1 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #2 CPUTYPE P3041 2 0 ;Core#2 / SOC#0 #2 EDBCR0 EDM DNH EFT ;set run parameters #2 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #3 CPUTYPE P3041 3 0 ;Core#3 / SOC#0 #3 EDBCR0 EDM DNH EFT ;set run parameters #3 STARTUP HALT ;halt at the reset vector ; [HOST] IP 151.120.25.112 FILE E:\temp\dump1024k.bin FORMAT BIN 0x80000000 ; #0 PROMPT P3041#0> #1 PROMPT P3041#1> #2 PROMPT P3041#2> #3 PROMPT P3041#3> ; [FLASH] ;flash is S29GL01GP WORKSPACE 0x80001000 ;workspace in CPC1/SRAM CHIPTYPE MIRRORX16 ;Flash type is S29GL01GP CHIPSIZE 0x08000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits FILE E:\temp\dump256k.bin FORMAT BIN 0xed800000 ERASE 0xed800000 0x20000 4 [REGS] FILE $regP3041.def