;bdiGDB configuration file for P2041-RDB ;--------------------------------------- ; ; [INIT] ; ; Setup TLB1 ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX WTLB 0x80000900_0xe000000a 0x10020000_0xe000003f ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX WTLB 0x80000a00_0x40000000 0x10040000_0x4000003f ;1/4: 40000000->0_40000000 1GB ----- RWXRWX WTLB 0x80000500_0x80000000 0x10050000_0x8000003f ;1/5: 80000000->0_80000000 1MB ----- RWXRWX ; ;========================================================================================= ; Setup TLB0 (for test purpose only) ; MAS1 MAS2 MAS0/MAS7 MAS3 WTLB 0x80000100_0xc0000000 0x00000000_0x0000003f ;WAY0: c0000000->0_00000000 4KB ----- RWXRWX WTLB 0x80000100_0xc0001000 0x00000000_0x0000103f ;WAY0: c0001000->0_00001000 4KB ----- RWXRWX WTLB 0x80000100_0xc0002000 0x00000000_0x0000203f ;WAY0: c0002000->0_00002000 4KB ----- RWXRWX WTLB 0x80000100_0xc0003000 0x00000000_0x0000303f ;WAY0: c0003000->0_00003000 4KB ----- RWXRWX ;========================================================================================= ; ; Initialize LAWBAR's WM32 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 WM32 0xfe000c04 0xe0000000 WM32 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB ; WM32 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 WM32 0xfe000c14 0x80000000 WM32 0xfe000c18 0x81000013 ;LAWAR1 : DDR1/CPC1 1MB ; WM32 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 WM32 0xfe000df4 0x00000000 WM32 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; ; Use L3 cache (CPC1) as SRAM at 0x80000000 WM32 0xfe010100 0x00000000 ;CPC1_SRCR1 : high address WM32 0xfe010104 0x8000000b ;CPC1_SRCR0 : all 32 ways as SRAM WM32 0xfe010000 0x80000000 ;CPC1_CSR0 : CPC enable WM32 0xfe010f00 0x08000000 ;CPC1_HDBCR0: Speculation disable ; ; Local Bus Controller WM32 0xfe124004 0xf8000f85 ;OR0: Flash WM32 0xfe124000 0xe8001001 ;BR0: ; ; Setup DDR3 WM32 0xfe008000 0x000000ff ;CS0_BNDS WM32 0xfe008008 0x00000000 ;CS1_BNDS WM32 0xfe008010 0x00000000 ;CS2_BNDS WM32 0xfe008018 0x00000000 ;CS3_BNDS WM32 0xfe008080 0x80044302 ;CS0_CONFIG WM32 0xfe008084 0x80004302 ;CS1_CONFIG WM32 0xfe008088 0x00000000 ;CS2_CONFIG WM32 0xfe00808c 0x00000000 ;CS3_CONFIG WM32 0xfe0080C0 0x00000000 ;CS0_CONFIG_2 WM32 0xfe0080C4 0x00000000 ;CS1_CONFIG_2 WM32 0xfe0080C8 0x00000000 ;CS2_CONFIG_2 WM32 0xfe0080Cc 0x00000000 ;CS3_CONFIG_2 WM32 0xfe008100 0x01061000 ;TIMING_CFG_3 WM32 0xfe008104 0x50110104 ;TIMING_CFG_0 WM32 0xfe008108 0x98913a45 ;TIMING_CFG_1 WM32 0xfe00810C 0x0fb8a8d4 ;TIMING_CFG_2 WM32 0xfe008110 0x47044000 ;DDR_CFG WM32 0xfe008114 0x24401110 ;DDR_CFG_2 WM32 0xfe008118 0x00441a50 ;DDR_MODE WM32 0xfe00811C 0x00100000 ;DDR_MODE_2 WM32 0xfe008200 0x00001a50 ;DDR_MODE_3 WM32 0xfe008204 0x00100000 ;DDR_MODE_4 WM32 0xfe008208 0x00001a50 ;DDR_MODE_5 WM32 0xfe00820c 0x00100000 ;DDR_MODE_6 WM32 0xfe008210 0x00001a50 ;DDR_MODE_7 WM32 0xfe008214 0x00100000 ;DDR_MODE_8 WM32 0xfe008124 0x14500100 ;DDR_INTERVAL WM32 0xfe008128 0xdeadbeef ;DDR_DATA_INIT WM32 0xfe008130 0x02800000 ;DDR_CLK_CNTL WM32 0xfe008148 0x00000000 ;DDR_INIT_ADDR WM32 0xfe00814C 0x00000000 ;DDR_INIT_EXT_ADDR WM32 0xfe008160 0x00000001 ;TIMING_CFG_4 WM32 0xfe008164 0x03401400 ;TIMING_CFG_5 WM32 0xfe008170 0x89080600 ;DDR_ZQ_CNTL WM32 0xfe008174 0x8675f607 ;DDR_WRLVL_CNTL WM32 0xfe008B28 0x80000000 ;DDRCDR_1 WM32 0xfe008B2C 0x00000000 ;DDRCDR_2 DELAY 100 WM32 0xfe008110 0xc7044000 ;DDR_CFG DELAY 1000 ; ; ; Setup TLB1 for core #0,#1,#2,#3 ; MAS1 MAS2 MAS0/MAS7 MAS3 #1 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #1 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX #1 WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX #2 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #2 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX #2 WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX #3 WTLB 0x80000700_0xfe00000a 0x10010000_0xfe00003f ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX #3 WTLB 0x80000500_0x80000000 0x10020000_0x8000003f ;1/2: 80000000->0_80000000 1MB ----- RWXRWX #3 WTLB 0x80000a00_0x00000000 0x10030000_0x0000003f ;1/3: 00000000->0_00000000 1GB ----- RWXRWX ; ; write DNH instruction to default vector WM32 0x80000000 0x4c00018c ;catch default vector ; ; write a loop to CPC1/SRAM WM32 0x80000100 0x386003e8 ;li r3,1000 WM32 0x80000104 0x38800000 ;li r4,0 WM32 0x80000108 0x38a00000 ;li r5,0 WM32 0x8000010c 0x38a50008 ;addi r5,r5,8 WM32 0x80000110 0x38840008 ;addi r4,r4,8 WM32 0x80000114 0x3463ffff ;addic. r3,r3,-1 WM32 0x80000118 0x4082fff4 ;bne bc WM32 0x8000011c 0x4bffffe4 ;b b0 WM32 0x80000120 0x60000000 ;nop WM32 0x80000124 0x60000000 ;nop ; ; set PC to start of loop #0 WREG pc 0x80000100 #1 WREG pc 0x80000100 #2 WREG pc 0x80000100 #3 WREG pc 0x80000100 ; ; set default vector #0 WREG ivpr 0x80000000 #1 WREG ivpr 0x80000000 #2 WREG ivpr 0x80000000 #3 WREG ivpr 0x80000000 ; ; Release cores for booting WREG brr 0x0000000f ;BRR: release cores ; [TARGET] ; common parameters POWERUP 5000 ;start delay after power-up detected in ms JTAGCLOCK 1 ;BDI3000: use 16 MHz JTAG clock ;JTAGCLOCK 0 ;BDI2000: use 16 MHz JTAG clock RESET HARD 1000 ;assert reset for 0.5 seconds WAKEUP 500 ;give reset time to complete ;MEMACCESS SAP 10 ;memory access via SAP (10us access delay) ; ;======================================================== ; !!!! define the core ID (the #x) without any holes !!!! ; !!!! no need that core ID matches the core number !!!! ; !!!! A valid example is: #1 CPUTYPE P4080 5 0 !!!! ;======================================================== ; ; CoreID#0 parameters (active vCPU after reset) #0 CPUTYPE P2041 0 0 ;Core#0 / SOC#0 #0 EDBCR0 EDM DNH EFT ;set run parameters #0 STARTUP HALT ;halt at the reset vector (this halts all cores !!!) #0 BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint #0 STEPMODE HWBP ;ICMP or HWBP, HWBP uses a hardware breakpoint ; ; RCW Override for SOC#0 assigned to CoreID#0 ; don't override PLL configuration in RCW[0]-RCW[3] ;#0 RCWSRC 0x18 ;Hard-Coded RCW 1_1000 ;#0 RCWOVR 0 0x4c140000 ; 0: don't override !!! ;#0 RCWOVR 1 0x00000000 ; 32: don't override !!! ;#0 RCWOVR 2 0x12121414 ; 64: don't override !!! ;#0 RCWOVR 3 0x00008888 ; 96: don't override !!! ;#0 RCWOVR 4 0x00000000 ;128: ;#0 RCWOVR 5 0x00000000 ;160: ;#0 RCWOVR 6 0xfe800000 ;192: ;#0 RCWOVR 7 0x01000000 ;224: ;#0 RCWOVR 8 0x00000000 ;256: ;#0 RCWOVR 9 0x00000000 ;288: ;#0 RCWOVR 10 0x00000000 ;320: ;#0 RCWOVR 11 0x00070100 ;352: ;#0 RCWOVR 12 0x00000000 ;384: ;#0 RCWOVR 13 0x00000000 ;416: ;#0 RCWOVR 14 0x00000000 ;448: ;#0 RCWOVR 15 0x00000000 ;480: ; ; ; CoreID#1 parameters #1 CPUTYPE P2041 1 0 ;Core#1 / SOC#0 #1 EDBCR0 EDM DNH EFT ;set run parameters #1 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #2 CPUTYPE P2041 2 0 ;Core#2 / SOC#0 #2 EDBCR0 EDM DNH EFT ;set run parameters #2 STARTUP HALT ;halt at the reset vector ; ; CoreID#1 parameters #3 CPUTYPE P2041 3 0 ;Core#3 / SOC#0 #3 EDBCR0 EDM DNH EFT ;set run parameters #3 STARTUP HALT ;halt at the reset vector ; [HOST] FILE E:\temp\dump1024k.bin FORMAT BIN 0x80000000 ; #0 PROMPT P2041#0> #1 PROMPT P2041#1> #2 PROMPT P2041#2> #3 PROMPT P2041#3> ; [FLASH] ;flash is S29GL01GP WORKSPACE 0x80001000 ;workspace in CPC1/SRAM CHIPTYPE MIRRORX16 ;Flash type is S29GL01GP CHIPSIZE 0x08000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits FILE E:\temp\dump256k.bin FORMAT BIN 0xe9000000 ERASE 0xe9000000 0x20000 4 [REGS] FILE $regP2041.def