;bdiGDB configuration file for P2020DS SMP Mode ;---------------------------------------------- ; ; The values used to configure the memory controller ; are the ones U-boot uses to setup my system. ; Your system may need different ones !!! ; ; This configuration is not usable for U-boot debugging. ; Use it to debug example code loaded into SDRAM. ; ; [INIT] ; ;================= seems to be necessary =============== ; Move the 256kB L2SRAM to the initial MMU page WREG l2errdis 0x0000001C ;L2ERRDIS: disable parity error WREG l2ctl 0x60010000 ;L2CTL WREG l2srbar0 0xFFF80000 ;L2SRBAR0: map to 0x0_FFF80000 WREG l2srbarea0 0x00000000 ;L2SRBAREA0 WREG l2ctl 0xA0010000 ;L2CTL ; ; load and execute some boot code WM32 0xfffffffc 0x48000000 ;loop #0 EXEC 0xfffffffc #1 EXEC 0xfffffffc ; ; Remove the L2SRAM from the initial MMU page WREG l2ctl 0x10010000 ;L2CTL WREG l2ctl 0x10000000 ;L2CTL ; ;================= setup TLB entries =================== ; ; +--------+--------+ +--------------------+-+-+-+-----+----+ ; | TID |IDX/WAY | | EPN |T|I|S|WIMGE|SIZE| ; +--------+--------+ +--------------------+-+-+-+-----+----+ ; 8 8 20 1 1 1 5 4 ; A size of 0 selects TLB0. T is TS / I is IPROT / S is SHAREN ; +----+ +--------------------+----+---+---+--+ ; |ERPN| | RPN |USER|UUU|SSS|XX| ; | | | |ATTR|RWX|RWX|01| ; +----+ +--------------------+----+---+---+--+ ; 4 20 4 3 3 2 ; To invalidate an entry set UUUSSSXX all 0 ; ; 64 MB TLB1 #0 0xfc000000 - 0xffffffff #0 WTLB 0_0xfc0000a8 0xfc00001c #1 WTLB 0_0xfc0000a8 0xfc00001c ; ; 1 GB TLB1 #1 0x80000000 - 0xbfffffff #0 WTLB 1_0x800000aa 0x8000001c #1 WTLB 1_0x800000aa 0x8000001c ; ; 256 MB TLB1 #2 0xe0000000 - 0xefffffff #0 WTLB 2_0xe00000a9 0xe000001c #1 WTLB 2_0xe00000a9 0xe000001c ; ; 256 MB TLB1 #3 0xc0000000 - 0xcfffffff #0 WTLB 3_0xc00000a9 0xc000001c #1 WTLB 3_0xc00000a9 0xc000001c ; ; 256 MB TLB1 #4 0xd0000000 - 0xdfffffff #0 WTLB 4_0xd00000a9 0xd000001c #1 WTLB 4_0xd00000a9 0xd000001c ; ; 1 GB TLB1 #5 0x00000000 - 0x3fffffff #0 WTLB 5_0x000000aa 0x0000001c #1 WTLB 5_0x000000aa 0x0000001c ; ; 1 GB TLB1 #6 0x40000000 - 0x7fffffff #0 WTLB 6_0x400000aa 0x4000001c #1 WTLB 6_0x400000aa 0x4000001c ; ;================= end setup TLB entries ===================== ; ; ;================= setup memory controller =================== ; Let CCSRBAR at 0xff700000 ;WREG ccsrbar 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WREG lawbar0 0x00000000 ;LAWBAR0 : @0x00000000 WREG lawar0 0x80f0001e ;LAWAR0 : DDR/SDRAM 2GB WREG lawbar1 0x000c0000 ;LAWBAR1 : @0xc0000000 WREG lawar1 0x8040001d ;LAWAR1 : Local Bus 1GB WREG lawbar2 0x00080000 ;LAWBAR2 : @0x80000000 WREG lawar2 0x8000001d ;LAWAR2 : PCI 1GB ; ; Setup chip select WREG or0 0xf8000ff7 ;OR0 : Flash WREG br0 0xe8001001 ;BR0 : 128MB at 0xe8000000 ; ; Setup DDR2 WREG cs0_bnds 0x0000003f ;CS0_BNDS WREG cs1_bnds 0x0040007f ;CS1_BNDS WREG cs2_bnds 0x00000000 ;CS2_BNDS WREG cs3_bnds 0x00000000 ;CS3_BNDS WREG cs0_config 0x80044202 ;CS0_CONFIG WREG cs1_config 0x80004202 ;CS1_CONFIG WREG cs2_config 0x00000000 ;CS2_CONFIG WREG cs3_config 0x00000000 ;CS3_CONFIG WREG cs0_config_2 0x00000000 ;CS0_CONFIG_2 WREG cs1_config_2 0x00000000 ;CS1_CONFIG_2 WREG cs2_config_2 0x00000000 ;CS2_CONFIG_2 WREG cs3_config_2 0x00000000 ;CS3_CONFIG_2 WREG timing_cfg_3 0x00010000 ;TIMING_CFG_3 WREG timing_cfg_0 0x00660804 ;TIMING_CFG_0 WREG timing_cfg_1 0x5d5bd533 ;TIMING_CFG_1 WREG timing_cfg_2 0x0fa888cd ;TIMING_CFG_2 WREG ddr_cfg 0x47000000 ;DDR_CFG WREG ddr_cfg_2 0x24401011 ;DDR_CFG_2 WREG ddr_mode 0x00421222 ;DDR_MODE WREG ddr_mode_2 0x04000000 ;DDR_MODE_2 WREG ddr_mode_cntl 0x00000000 ;DDR_MODE_CNTL WREG ddr_interval 0x0a280100 ;DDR_INTERVAL WREG ddr_data_init 0xdeadbeef ;DDR_DATA_INIT WREG ddr_clk_cntl 0x02000000 ;DDR_CLK_CNTL WREG ddr_init_addr 0x00000000 ;DDR_INIT_ADDR WREG ddr_init_eaddr 0x00000000 ;DDR_INIT_EXT_ADDR WREG timing_cfg_4 0x00220001 ;TIMING_CFG_4 WREG timing_cfg_5 0x03402400 ;TIMING_CFG_5 WREG ddr_zq_cntl 0x00000000 ;DDR_ZQ_CNTL WREG ddr_wrlvl_cntl 0x8645f607 ;DDR_WRLVL_CNTL WREG ddrcdr_1 0x00000000 ;DDRCDR_1 WREG ddrcdr_2 0x00000000 ;DDRCDR_2 DELAY 100 WREG ddr_cfg 0xc7000000 ;DDR_CFG DELAY 1000 ; ;================= end setup memory controller =============== ; ; Setup debug vector for program execution WREG ivpr 0x00000000 ;IVPR : Exceptions at 0x00000000 WREG ivor6 0x0000700 ;IVOR6 : Program exception WREG ivor15 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; ; Test code in RAM WM32 0x00020100 0x3c6005f6 ;lis r3,1526 (100'000'000) WM32 0x00020104 0x38800000 ;li r4,0 WM32 0x00020108 0x38a00000 ;li r5,0 WM32 0x0002010c 0x38a50008 ;addi r5,r5,8 WM32 0x00020110 0x38840008 ;addi r4,r4,8 WM32 0x00020114 0x3463ffff ;addic. r3,r3,-1 WM32 0x00020118 0x4082fff4 ;bne bc WM32 0x0002011c 0x4bffffe4 ;b b0 WM32 0x00020120 0x60000000 ;nop WM32 0x00020124 0x60000000 ;nop ; #0 WREG pc 0x00020100 ;set PC #1 WREG pc 0x00020100 ;set PC [TARGET] CPUTYPE P2020 ;the CPU type JTAGCLOCK 16000000 ;use 16 MHz JTAG clock STARTUP HALT HALT SMP ;halt both cores at boot vector, SMP mode BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG, ICMP or HWBP, HWPB uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [HOST] PROMPT P2020SMP> FILE E:\temp\dump1024k.bin FORMAT BIN 0x00010000 [FLASH] [REGS] FILE $regP2020.def