;bdiGDB configuration file for P2020-DS ;-------------------------------------- ; ; The values used to configure the memory controller ; are the ones U-boot uses to setup my system. ; Your system may need different ones !!! ; ; This configuration is not usable for U-boot debugging. ; Use it to debug example code loaded into SDRAM. ; ; [INIT] ; ;================= setup TLB entries =================== ; Move the L2SRAM to the initial MMU page WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error WM32 0xFF720000 0x60010000 ;L2CTL WM32 0xFF720100 0xFFF80000 ;L2SRBAR0: map to 0x0_FFF80000 WM32 0xFF720104 0x00000000 ;L2SRBAREA0 WM32 0xFF720000 0xA0010000 ;L2CTL ; ; load and execute some boot code WM32 0xfffffffc 0x48000000 ;loop EXEC 0xfffffffc ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop WSPR 628 0x00000000 ;MAS4: WSPR 630 0x00000000 ;MAS7: ; ; 64 MB TLB1 #0 0xfc000000 - 0xffffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xfc00000a ;MAS2: WSPR 627 0xfc000015 ;MAS3: EXEC 0xfffff000 ; ; 1 GB TLB1 #1 0x80000000 - 0xbfffffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000a00 ;MAS1: WSPR 626 0x8000000a ;MAS2: WSPR 627 0x80000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #2 0xe0000000 - 0xefffffff WSPR 624 0x10020000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0xe000000a ;MAS2: WSPR 627 0xe0000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #3 0xc0000000 - 0xcfffffff WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80000900 ;MAS1: WSPR 626 0xc000000a ;MAS2: WSPR 627 0xc0000015 ;MAS3: EXEC 0xfffff000 ; ; 256 MB TLB1 #4 0xd0000000 - 0xdfffffff WSPR 624 0x10040000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xd000000a ;MAS2: WSPR 627 0xd0000015 ;MAS3: EXEC 0xfffff000 ; ; 1 GB TLB1 #5 0x00000000 - 0x3fffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000a00 ;MAS1: WSPR 626 0x00000000 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 1 GB TLB1 #6 0x40000000 - 0x7fffffff WSPR 624 0x10060000 ;MAS0: WSPR 625 0x80000a00 ;MAS1: WSPR 626 0x40000000 ;MAS2: WSPR 627 0x40000015 ;MAS3: EXEC 0xfffff000 ; ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x20010000 ;L2CTL WM32 0xFF720000 0x20000000 ;L2CTL ;================= end setup TLB entries ===================== ; ; ;================= setup memory controller =================== ; Let CCSRBAR at 0xff700000 ;WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xff700C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xff700C10 0x80f0001e ;LAWAR0 : DDR/SDRAM 2GB WM32 0xff700C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0xff700C30 0x8040001d ;LAWAR1 : Local Bus 1GB WM32 0xff700C48 0x00080000 ;LAWBAR2 : @0x80000000 WM32 0xff700C50 0x8000001d ;LAWAR2 : PCI 1GB ; ; Setup chip select WM32 0xff705004 0xf8000ff7 ;OR0 : Flash WM32 0xff705000 0xe8001001 ;BR0 : 128MB at 0xe8000000 WM32 0xff70500C 0xf8000ff7 ;OR1 : Flash WM32 0xff705008 0xe0001001 ;BR1 : 128KB at 0xe0000000 ; ; Setup DDR3 WM32 0xff702000 0x0000003f ;CS0_BNDS WM32 0xff702008 0x0040007f ;CS1_BNDS WM32 0xff702010 0x00000000 ;CS2_BNDS WM32 0xff702018 0x00000000 ;CS3_BNDS WM32 0xff702080 0x80044202 ;CS0_CONFIG WM32 0xff702084 0x80004202 ;CS1_CONFIG WM32 0xff702088 0x00000000 ;CS2_CONFIG WM32 0xff70208C 0x00000000 ;CS3_CONFIG WM32 0xff7020C0 0x00000000 ;CS0_CONFIG_2 WM32 0xff7020C4 0x00000000 ;CS1_CONFIG_2 WM32 0xff7020C8 0x00000000 ;CS2_CONFIG_2 WM32 0xff7020CC 0x00000000 ;CS3_CONFIG_2 WM32 0xff702100 0x00010000 ;TIMING_CFG_3 WM32 0xff702104 0x00660804 ;TIMING_CFG_0 WM32 0xff702108 0x5d5bd533 ;TIMING_CFG_1 WM32 0xff70210C 0x0fa888cd ;TIMING_CFG_2 WM32 0xff702110 0x47000000 ;DDR_CFG WM32 0xff702114 0x24401011 ;DDR_CFG_2 WM32 0xff702118 0x00421222 ;DDR_MODE WM32 0xff70211C 0x04000000 ;DDR_MODE_2 WM32 0xff702124 0x0a280100 ;DDR_INTERVAL WM32 0xff702128 0xdeadbeef ;DDR_DATA_INIT WM32 0xff702130 0x02000000 ;DDR_CLK_CNTL WM32 0xff702148 0x00000000 ;DDR_INIT_ADDR WM32 0xff70214C 0x00000000 ;DDR_INIT_EXT_ADDR WM32 0xff702160 0x00220001 ;TIMING_CFG_4 WM32 0xff702164 0x03402400 ;TIMING_CFG_5 WM32 0xff702170 0x00000000 ;DDR_ZQ_CNTL WM32 0xff702174 0x8645f607 ;DDR_WRLVL_CNTL ;WM32 0xff70217C 0x00000000 ;DDR_SR_CNTR ;WM32 0xff702180 0x00000000 ;DDR_SDRAM_RCW_1 ;WM32 0xff702184 0x00000000 ;DDR_SDRAM_RCW_2 WM32 0xff702B28 0x00000000 ;DDRCDR_1 WM32 0xff702B2C 0x00000000 ;DDRCDR_2 DELAY 100 WM32 0xff702110 0xc7000000 ;DDR_CFG DELAY 1000 ; ;================= end setup memory controller =============== ; ; Setup debug vector for program execution WSPR 63 0x00000000 ;IVPR : Exceptions at 0x00000000 WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; [TARGET] CPUTYPE P2020 ;the CPU type JTAGCLOCK 1 ;use 16MHz JTAG clock STARTUP HALT ;halt core #0 at boot vector ;STARTUP HALT HALT ;halt both core at the reset vector BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWPB uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [HOST] IP 151.120.25.112 PROMPT P2020> FILE E:\temp\dump1024k.bin FORMAT BIN 0x00010000 [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;Chipsize is 128MB BUSWIDTH 16 WORKSPACE 0x00010000 ;workspace in DDR SDRAM FILE E:\temp\dump256k.bin FORMAT BIN 0xec000000 ERASE 0xec000000 0x20000 4 ;erase 4 sectors [REGS] FILE $regP2020.def