;bdiGDB configuration file for P1020 in little endian mode
;---------------------------------------------------------
;
;
[INIT]
;
;================= seems to be necessary ===============
; Move the 256kB L2SRAM to the initial MMU page
WREG    l2errdis        0x0000001C      ;L2ERRDIS: disable parity error
WREG    l2ctl           0x50010000      ;L2CTL
WREG    l2srbar0        0xFFFC0000      ;L2SRBAR0: map to 0x0_FFFC0000
WREG    l2srbarea0      0x00000000      ;L2SRBAREA0
WREG    l2ctl           0x90010000      ;L2CTL
;
; load and execute some boot code
WM32    0xfffffffc      0x00000048      ;loop (little endian)
EXEC    0xfffffffc
;
; Remove the L2SRAM from the initial MMU page
WREG    l2ctl           0x10010000      ;L2CTL
WREG    l2ctl           0x10000000      ;L2CTL
;
;================= setup TLB entries ===================
;
;   +--------+--------+ +--------------------+-+-+-+-----+----+
;   |  TID   |IDX/WAY | |          EPN       |T|I|S|WIMGE|SIZE|
;   +--------+--------+ +--------------------+-+-+-+-----+----+
;       8        8                 20         1 1 1   5     4
;
;   +----+ +--------------------+----+---+---+--+
;   |ERPN| |          RPN       |USER|UUU|SSS|XX|
;   |    | |                    |ATTR|RWX|RWX|01|
;   +----+ +--------------------+----+---+---+--+
;     4               20          4    3   3   2
;
; 64 MB TLB1 #0 0xfc000000 - 0xffffffff
WTLB 0_0xfc0000a8    0xfc00001c
;
; 1 GB  TLB1 #1 0x80000000 - 0xbfffffff (LE)
WTLB 1_0x800000ba    0x8000001c
;
; Move the 256kB L2SRAM to 0x80000000 (LE)
WREG    l2errdis        0x0000001C      ;L2ERRDIS: disable parity error
WREG    l2ctl           0x50010000      ;L2CTL
WREG    l2srbar0        0x80000000      ;L2SRBAR0: map to 0x0_FFFC0000
WREG    l2srbarea0      0x00000000      ;L2SRBAREA0
WREG    l2ctl           0x90010000      ;L2CTL
;
; Setup debug vector for program execution
WREG    ivpr            0x80000000      ;IVPR   : Exceptions at 0x80000000
WREG    ivor6           0x00000000      ;IVOR6  : Program exception
WREG    ivor15          0x00000000      ;IVOR15 : Debug exception
WM32    0x80000000      0x48000000      ;write valid instruction
;
; Test code in RAM
WM32    0x80000100      0x3c6005f6      ;lis    r3,1526 (100'000'000)
WM32    0x80000104      0x38800000      ;li     r4,0
WM32    0x80000108      0x38a00000      ;li     r5,0
WM32    0x8000010c      0x38a50008      ;addi   r5,r5,8
WM32    0x80000110      0x38840008      ;addi   r4,r4,8
WM32    0x80000114      0x3463ffff      ;addic. r3,r3,-1
WM32    0x80000118      0x4082fff4      ;bne    bc <TestLoop>
WM32    0x8000011c      0x4bffffe4      ;b      b0 <Test>
WM32    0x80000120      0x60000000      ;nop
WM32    0x80000124      0x60000000      ;nop
;
WREG pc                 0x80000100      ;set PC
;


[TARGET]
CPUTYPE     P1020       ;the CPU type
ENDIAN      LITTLE
JTAGCLOCK   16000000    ;use 16 MHz JTAG clock
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWPB uses a hardware breakpoint
WAKEUP      200         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms
REGLIST     E500


[HOST]
PROMPT      1020LE>


[FLASH]


[REGS]
FILE        $regP1020LE.def     ;little endian variant