; bdiGDB configuration file for TQM855L/TQM860L Modules ; ----------------------------------------------------- ; [INIT] ; init core register WREG MSR 0x00001002 ;MSR : ME,RI WSPR 27 0x00001002 ;SRR1 : ME,RI ;;WSPR 149 0x2002000F ;DER : set debug enable register WSPR 149 0x2006000F ;DER : enable SYSIE for BDI flash progr. WSPR 638 0xFFF00000 ;IMMR : internal memory at 0xFFF00000 WSPR 158 0x00000007 ;ICTRL: ; init SIU register WM32 0xFFF00000 0x01610400 ;SIUMCR WM32 0xFFF00004 0xFFFFFF88 ;SYPCR ;WM32 0xFFF00284 0x00000000 ;PLPRCR no need to change (1:1 clock mode) ; init UPM ; SUPM 0xFFF00168 0xFFF0017c ;set address for MCR and MDR ; ; single read. (offset 0 in UPMA RAM) ; WUPM 0x00000000 0x1F0DFC04 ;UPMA single read WUPM 0x00000001 0xEEAFBC04 WUPM 0x00000002 0x11AF7C04 WUPM 0x00000003 0xEFBAFC00 WUPM 0x00000004 0x1FF5FC47 ;last ; ; SDRAM initialization (offset 5 in UPMA RAM) ; WUPM 0x00000005 0x1FF5FC34 WUPM 0x00000006 0xEFEABC34 WUPM 0x00000007 0x1FB57C35 ;last ; ; burst read. (offset 8 in UPMA RAM) ; WUPM 0x00000008 0x1F0DFC04 WUPM 0x00000009 0xEEAFBC04 WUPM 0x0000000A 0x10AF7C04 WUPM 0x0000000B 0xF0AFFC00 WUPM 0x0000000C 0xF0AFFC00 WUPM 0x0000000D 0xF1AFFC00 WUPM 0x0000000E 0xEFBAFC00 WUPM 0x0000000F 0x1FF5FC47 ;last WUPM 0x00000010 0xFFFFFFFF WUPM 0x00000011 0xFFFFFFFF WUPM 0x00000012 0xFFFFFFFF WUPM 0x00000013 0xFFFFFFFF WUPM 0x00000014 0xFFFFFFFF WUPM 0x00000015 0xFFFFFFFF WUPM 0x00000016 0xFFFFFFFF WUPM 0x00000017 0xFFFFFFFF ; ; single write. (offset 18 in UPMA RAM) ; WUPM 0x00000018 0x1F2DFC04 WUPM 0x00000019 0xEEABBC00 WUPM 0x0000001A 0x01B27C04 WUPM 0x0000001B 0x1FF5FC47 ;last WUPM 0x0000001C 0xFFFFFFFF WUPM 0x0000001D 0xFFFFFFFF WUPM 0x0000001E 0xFFFFFFFF WUPM 0x0000001F 0xFFFFFFFF ; ; burst write. (offset 20 in UPMA RAM) ; WUPM 0x00000020 0x1F0DFC04 WUPM 0x00000021 0xEEABBC00 WUPM 0x00000022 0x10A77C00 WUPM 0x00000023 0xF0AFFC00 WUPM 0x00000024 0xF0AFFC00 WUPM 0x00000025 0xE1BAFC04 WUPM 0x00000026 0x1FF5FC47 ;last WUPM 0x00000027 0xFFFFFFFF WUPM 0x00000028 0xFFFFFFFF WUPM 0x00000029 0xFFFFFFFF WUPM 0x0000002A 0xFFFFFFFF WUPM 0x0000002B 0xFFFFFFFF WUPM 0x0000002C 0xFFFFFFFF WUPM 0x0000002D 0xFFFFFFFF WUPM 0x0000002E 0xFFFFFFFF WUPM 0x0000002F 0xFFFFFFFF ; ; refresh (offset 30 in UPMA RAM) ; WUPM 0x00000030 0x1FFD7C84 WUPM 0x00000031 0xFFFFFC04 WUPM 0x00000032 0xFFFFFC04 WUPM 0x00000033 0xFFFFFC04 WUPM 0x00000034 0xFFFFFC84 WUPM 0x00000035 0xFFFFFC07 ;last WUPM 0x00000036 0xFFFFFFFF WUPM 0x00000037 0xFFFFFFFF WUPM 0x00000038 0xFFFFFFFF WUPM 0x00000039 0xFFFFFFFF WUPM 0x0000003A 0xFFFFFFFF WUPM 0x0000003B 0xFFFFFFFF ; ; exception. (offset 3c in UPMA RAM) ; WUPM 0x0000003C 0x7FFFFC07 ;last WUPM 0x0000003D 0xFFFFFFFF WUPM 0x0000003E 0xFFFFFFFF WUPM 0x0000003F 0xFFFFFFFF ; Init Memory Controller: ; ; BR0/1 and OR0/1 (FLASH) WM32 0xFFF00104 0xFFC00F52 ; 4 MB --> was: 0xE0000F52 ; WM32 0xFFF00100 0x40000001 ; @ 0x40000000 WM32 0xFFF0010C 0xFFC00F52 ; 4 MB ; was: 0xE0000F52 ; since Rev. 200: 0E0000F50 WM32 0xFFF00108 0x40400001 ; @ 0x40400000 --> was: 0x60000001 ; BR2/3 and OR2/3 (SDRAM) WM32 0xFFF00114 0xE0000B00 WM32 0xFFF00110 0x00000081 WM32 0xFFF0011C 0xE0000B00 WM32 0xFFF00118 0x20000081 ; BR4 and OR4 (SRAM) WM32 0xFFF00124 0xE0000D40 WM32 0xFFF00120 0x80000001 WM32 0xFFF00170 0xC3802114 ; MAMR = machine A mode register ; Initialize memory periodic timer prescaler (MPTPR). ; Preliminary prescaler for refresh (depends on number of banks). ; This value is selected for four cycles every 62.4 us with two SDRAM ; banks or four cycles every 31.2 us with one bank. It will be adjusted ; after memory sizing. WM16 0xFFF0017A 0x1000 WM32 0xFFF00164 0x00000088 ; MAR = Memory Address Register ; Execute precharge-all command using Memory Command Register, Patch-Offset 5. ; Immediately following initialize SDRAM starting at Patch-Offset 7. ; ; Banks 0 and 1 WM32 0xFFF00168 0x80004105 WM32 0xFFF00168 0x80006105 ; ; 2 x 4fach-Refresh durchführen über Memory Command Register an Patch-Offset $30 ; WM32 0xFFF00168 0x80004130 WM32 0xFFF00168 0x80004130 WM32 0xFFF00168 0x80006130 WM32 0xFFF00168 0x80006130 [TARGET] CPUCLOCK 80000000 ;the CPU clock rate after processing the init list BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoints [HOST] IP 151.120.25.119 ;FILE E:\cygwin\home\bdidemo\mbx860\vmlinux ;FORMAT BIN ;FILE E:\cygwin\home\bdidemo\mbx860\zImage ;FORMAT IMAGE FILE E:\cygwin\home\bdidemo\mbx860\vxWorks FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset [FLASH] CHIPTYPE AM29BX16 ;Flash type (AM29LV160B) CHIPSIZE 0x200000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) WORKSPACE 0xFFF02000 ; RAM buffer for fast flash programming FILE /tftpboot/ppcboot.bin ;The file to program FORMAT BIN 0x40000000 ERASE 0x40000000 BLOCK ERASE 0x40008000 BLOCK ERASE 0x4000C000 BLOCK ERASE 0x40010000 BLOCK