; bdiGDB configuration file for RPXLite 850 SAR board
; ----------------------------------------------------
;
[INIT]
; init core register
;WREG    MSR             0x00001002      ;MSR  : ME,RI
;WSPR    27              0x00001002      ;SRR1 : ME,RI
;WSPR    149             0xFFE7400F      ;DER  : set debug enable register
;WSPR    149             0x2002000F      ;DER  : set debug enable register, for ;850?
WSPR    638             0xFA200000      ;IMMR : internal memory at 0xFA200000
WSPR    158             0x0000009E      ;ICTRL:

; init SIU register
WM32    0xFA200000      0x00000800      ;SIUMCR
WM32    0xFA200004      0xFFFFFF89      ;SYPCR
WM16    0xFA200200      0x00C3          ;TBSCR
WM32    0xFA200320      0x55CCAA33      ;RTCSCK: unlock real-time clock status and control register
WM16    0xFA200220      0x00C1          ;RTCSC
WM16    0xFA200240      0x0083          ;PTSCR

WM32    0xFA200284      0x0050D000      ;PLPRCR set clock to 16MHz (???)

; init UPM
SUPM    0xFA200168      0xFA20017c      ;set address for MCR and MDR
WUPM    0x00000000     	0xCFFFCC24      ;UPMA single read
WUPM    0x00000001      0x0FFFCC04
WUPM    0x00000002      0x0CAFCC04
WUPM    0x00000003      0x03AFCC08
WUPM    0x00000004      0x3FBFCC27	;last
WUPM    0x00000005      0xFFFFCC25      
WUPM    0x00000006      0xFFFFCC25
WUPM    0x00000007      0xFFFFCC25
WUPM    0x00000008      0xCFFFCC24      ;UPMA burst read
WUPM    0x00000009      0x0FFFCC04
WUPM    0x0000000A      0x0CAFCC84
WUPM    0x0000000B      0x03AFCC88
WUPM    0x0000000C      0x3FBFCC27	;last
WUPM    0x0000000D      0xFFFFCC25
WUPM    0x0000000E      0xFFFFCC25
WUPM    0x0000000F      0xFFFFCC25
WUPM    0x00000010      0xFFFFCC25
WUPM    0x00000011      0xFFFFCC25
WUPM    0x00000012      0xFFFFCC25
WUPM    0x00000013      0xFFFFCC25
WUPM    0x00000014      0xFFFFCC25      
WUPM    0x00000015      0xFFFFCC25
WUPM    0x00000016      0xFFFFCC25
WUPM    0x00000017      0xFFFFCC25
WUPM    0x00000018      0xCFFFCC24      ;UPMA single write
WUPM    0x00000019      0x0FFFCC04
WUPM    0x0000001A      0x0CFFCC04
WUPM    0x0000001B      0x03FFCC00      
WUPM    0x0000001C      0x3FFFCC27	;last
WUPM    0x0000001D      0xFFFFCC25
WUPM    0x0000001E      0xFFFFCC25
WUPM    0x0000001F      0xFFFFCC25
WUPM    0x00000020      0xCFFFCC24      ;UPMA burst write
WUPM    0x00000021      0x0FFFCC04
WUPM    0x00000022      0x0CFFCC80
WUPM    0x00000023      0x03FFCC8C
WUPM    0x00000024      0x0CFFCC00
WUPM    0x00000025      0x33FFCC27	;last
WUPM    0x00000026      0xFFFFCC25
WUPM    0x00000027      0xFFFFCC25
WUPM    0x00000028      0xFFFFCC25
WUPM    0x00000029      0xFFFFCC25	
WUPM    0x0000002A      0xFFFFCC25
WUPM    0x0000002B      0xFFFFCC25
WUPM    0x0000002C      0xFFFFCC25
WUPM    0x0000002D      0xFFFFCC25
WUPM    0x0000002E      0xFFFFCC25
WUPM    0x0000002F      0xFFFFCC25
WUPM    0x00000030      0xC0FFCC24      ;UPMA refresh
WUPM    0x00000031      0x03FFCC24
WUPM    0x00000032      0x0FFFCC24
WUPM    0x00000033      0x0FFFCC24
WUPM    0x00000034      0x3FFFCC27	;last
WUPM    0x00000035      0xFFFFCC25	
WUPM    0x00000036      0xFFFFCC25
WUPM    0x00000037      0xFFFFCC25
WUPM    0x00000038      0xFFFFCC25
WUPM    0x00000039      0xFFFFCC25
WUPM    0x0000003A      0xFFFFCC25
WUPM    0x0000003B      0xFFFFCC25
WUPM    0x0000003C      0xFFFFCC25      ;UPMA exception
WUPM    0x0000003D      0xFFFFCC25
WUPM    0x0000003E      0xFFFFCC25
WUPM    0x0000003F      0xFFFFCC25

; init memory controller
WM32    0xFA200104      0xFE000140      ;OR0
WM32    0xFA20010C      0xFF000E00      ;OR1
WM32    0xFA200114      0xFF000E00      ;OR2
WM32    0xFA200100      0xFE000001      ;BR0
WM32    0xFA200108      0x00000081      ;BR1
WM32    0xFA200110      0x00000000      ;BR2
WM16    0xFA20017A      0x0800          ;MPTPR : divide by 16
WM32    0xFA200170      0x58A01430      ;MAMR

WM32    0xFA200284      0x0050D000      ;PLPRCR set clock to 24MHz (???)


[TARGET]
CPUCLOCK    50000000    ;the CPU clock rate after processing the init list
BDIMODE     AGENT       ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   HARD        ;SOFT or HARD, HARD uses PPC hardware breakpoints

[HOST]
IP          192.168.1.36           ;slcmod
FILE        /tftpboot/rpxcllf      ;slcmod
FORMAT      ELF                    ;slcmod
LOAD        MANUAL        ;load code MANUAL or AUTO after reset
DEBUGPORT   2001

[FLASH]
CHIPTYPE    AM29BX8       ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x200000    ;The size of one flash chip in bytes (e.g. AM29F010 = 0x20000)
BUSWIDTH    32          ;The width of the flash memory bus in bits (8 | 16 | 32)
;FILE        C:\TEMP\BDI2000\ppc\  ;The file to program
;ERASE       0xFF800000  ;erase sector 0 of flash SIMM (MCM29F040)
;ERASE       0xFF810000  ;erase sector 1 of flash SIMM
;ERASE       0xFF818000  ;erase sector 2 of flash SIMM
;ERASE       0xFF820000  ;erase sector 3 of flash SIMM
;ERASE       0xFF840000  ;erase sector 4 of flash SIMM
;ERASE       0xFF880000  ;erase sector 5 of flash SIMM
;ERASE       0xFF9C0000  ;erase sector 6 of flash SIMM
;ERASE       0xFFA00000  ;erase sector 7 of flash SIMM

[REGS]
DMM1	0xFA200000
FILE    /tftpboot/reg860.def       ;slcmod