;Register definition for MPC850
;==============================
;
; name: user defined name of the register
; type: the type of the register
;	GPR	general purpose register
;	SPR	special purpose register
;	MM	memory mapped register
;	DMMx	direct memory mapped register with offset
;		x = 1..4
;		the base is defined in the configuration file
;		e.g. DMM1 0x02200000
; addr:	the number, adddress or offset of the register
; size	the size of the register (8,16 or 32)
;
;name		type	addr		size
;-------------------------------------------
;
; I don't know where this comes from
pc		SPR	26			; is srr0
;
; Table 4-2. from MPC850 manual
xer		SPR	1
lr		SPR	8
ctr		SPR	9
tblr		SPR	268
tbur		SPR	269
;
; Table 4-6.
dsisr		SPR	18
dar		SPR	19
dec		SPR	22
srr0		SPR	26
srr1		SPR	27
sprg0		SPR	272
sprg1		SPR	273
sprg2		SPR	274
sprg3		SPR	275
tblw		SPR	284
tbuw		SPR	285
pvr		SPR	287
;
; Table 4-9.
eie		SPR	80
eid		SPR	81
nri		SPR	82
dpir		SPR	631
immr		SPR	638
ic_cst		SPR	560
ic_adr		SPR	561
ic_dat		SPR	562
dc_cst		SPR	568
dc_adr		SPR	569
dc_dat		SPR	570
mi_ctr		SPR	784
mi_ap		SPR	786
mi_epn		SPR	787
mi_twc		SPR	789
mi_rpn		SPR	790
mi_cam		SPR	816
mi_ram0		SPR	817
mi_ram1		SPR	818
md_ctr		SPR	792
m_casid		SPR	793
md_ap		SPR	794
md_epn		SPR	795
m_twb		SPR	796
md_twc		SPR	797
md_rpn		SPR	798
m_tw		SPR	799
md_cam		SPR	824
md_ram0		SPR	825
md_ram1		SPR	826
;
; Table 4-10.
cmpa		SPR	144
cmpb		SPR	145
cmpc		SPR	146
cmpd		SPR	147
icr		SPR	148
der		SPR	149
counta		SPR	150
countb		SPR	151
cmpe		SPR	152
cmpf		SPR	153
cmpg		SPR	154
cmph		SPR	155
lctrl1		SPR	156
lctrl2		SPR	157
ictrl		SPR	158
bar		SPR	159
dpdr		SPR	630
;
; from regmpc860.def
sp		GPR	1
; ear             SPR     282
;
;
;
; DMM1 must be set to the internal memory base address
;
;       General SIU
siumcr		DMM1	0x000		32
sypcr		DMM1	0x004		32
; swt             DMM1    0x008
swsr            DMM1    0x00e           16
sipend          DMM1    0x010           32
simask          DMM1    0x014           32
siel            DMM1    0x018           32
sivec           DMM1    0x01c           32
tesr            DMM1    0x020           32
sdcr            DMM1    0x030           32
;
;       PCMCIA
pbr0            DMM1    0x080           32
por0            DMM1    0x084           32
pbr1            DMM1    0x088           32
por1            DMM1    0x08c           32
pbr2            DMM1    0x090           32
por2            DMM1    0x094           32
pbr3            DMM1    0x098           32
por3            DMM1    0x09c           32
pbr4            DMM1    0x0a0           32
por4            DMM1    0x0a4           32
pbr5            DMM1    0x0a8           32
por5            DMM1    0x0ac           32
pbr6            DMM1    0x0b0           32
por6            DMM1    0x0b4           32
pbr7            DMM1    0x0b8           32
por7            DMM1    0x0bc           32
; pgcra           DMM1    0x0e0           32
pgcrb           DMM1    0x0e4           32
pscr            DMM1    0x0e8           32
pipr            DMM1    0x0f0           32
per             DMM1    0x0f8           32
;
;       MEMC
br0             DMM1    0x100           32
or0             DMM1    0x104           32
br1             DMM1    0x108           32
or1             DMM1    0x10c           32
br2             DMM1    0x110           32
or2             DMM1    0x114           32
br3             DMM1    0x118           32
or3             DMM1    0x11c           32
br4             DMM1    0x120           32
or4             DMM1    0x124           32
br5             DMM1    0x128           32
or5             DMM1    0x12c           32
br6             DMM1    0x130           32
or6             DMM1    0x134           32
br7             DMM1    0x138           32
or7             DMM1    0x13c           32
mar             DMM1    0x164           32
mcr             DMM1    0x168           32
mamr            DMM1    0x170           32
mbmr            DMM1    0x174           32
mstat           DMM1    0x178           16
mptpr           DMM1    0x17a           16
mdr             DMM1    0x17c           32
;
;       System Integration Timer
tbscr           DMM1    0x200           16
tbrefa          DMM1    0x204           32
tbrefb          DMM1    0x208           32
rtcsc           DMM1    0x220           16
rtc             DMM1    0x224           32
rtsec           DMM1    0x228           32
rtcal           DMM1    0x22c           32
piscr           DMM1    0x240           16
pitc            DMM1    0x244           32
pitr            DMM1    0x248           32
;
;       Clocks and Reset
sccr            DMM1    0x280           32
plprcr          DMM1    0x284           32
rsr             DMM1    0x288           32
;
;       System Integration Timer Keys
tbscrk          DMM1    0x300           32
tbrefak         DMM1    0x304           32
tbrefbk         DMM1    0x308           32
tbk             DMM1    0x30c           32
rtcsck          DMM1    0x320           32
rtck            DMM1    0x324           32
rtseck          DMM1    0x328           32
rtcalk          DMM1    0x32c           32
piscrk          DMM1    0x340           32
pitck           DMM1    0x344           32
;
;       Clocks and Reset Keys
sccrk           DMM1    0x380           32
plprcrk         DMM1    0x384           32
rsrk            DMM1    0x388           32
;
;       I2C
i2mod           DMM1    0x860           8
i2add           DMM1    0x864           8
i2brg           DMM1    0x868           8
i2com           DMM1    0x86c           8
i2cer           DMM1    0x870           8
i2cmr           DMM1    0x874           8
;
;       DMA
sdar            DMM1    0x904           32
sdsr            DMM1    0x908           8
sdmr            DMM1    0x90c           8
idsr1           DMM1    0x910           8
idmr1           DMM1    0x914           8
idsr2           DMM1    0x918           8
idmr2           DMM1    0x91c           8
;
;       CPM Interrupt Control
civr            DMM1    0x930           16
cicr            DMM1    0x940           32
cipr            DMM1    0x944           32
cimr            DMM1    0x948           32
cisr            DMM1    0x94c           32
;
;       I/O Port
padir		DMM1	0x950		16
papar		DMM1	0x952		16
paodr		DMM1	0x954		16
padat		DMM1	0x956		16
pcdir           DMM1    0x960           16
pcpar           DMM1    0x962           16
pcso            DMM1    0x964           16
pcdat           DMM1    0x966           16
pcint           DMM1    0x968           16
pddir           DMM1    0x970           16
pdpar           DMM1    0x972           16
pddat           DMM1    0x976           16
;
;       CPM Timers
tgcr            DMM1    0x980           16
tmr1            DMM1    0x990           16
tmr2            DMM1    0x992           16
trr1            DMM1    0x994           16
trr2            DMM1    0x996           16
tcr1            DMM1    0x998           16
tcr2            DMM1    0x99a           16
tcn1            DMM1    0x99c           16
tcn2            DMM1    0x99e           16
tmr3            DMM1    0x9a0           16
tmr4            DMM1    0x9a2           16
trr3            DMM1    0x9a4           16
trr4            DMM1    0x9a6           16
tcr3            DMM1    0x9a8           16
tcr4            DMM1    0x9aa           16
tcn3            DMM1    0x9ac           16
tcn4            DMM1    0x9ae           16
ter1            DMM1    0x9b0           16
ter2            DMM1    0x9b2           16
ter3            DMM1    0x9b4           16
ter4            DMM1    0x9b6           16
;
;       Communications Proessor
cpcr            DMM1    0x9c0           16
rccr            DMM1    0x9c4           16
; res             DMM1    0x9c6           8
rmds            DMM1    0x9c7           8
; rmdr            DMM1    0x9c8           32
rctr1           DMM1    0x9cc           16
rctr2           DMM1    0x9ce           16
rctr3           DMM1    0x9d0           16
rctr4           DMM1    0x9d2           16
rter            DMM1    0x9d6           16
rtmr            DMM1    0x9da           16
;
;       BRGs
brgc1           DMM1    0x9f0           32
brgc2           DMM1    0x9f4           32
brgc3           DMM1    0x9f8           32
brgc4           DMM1    0x9fc           32
;
;       USB
usmod           DMM1    0xa00           8
usadr           DMM1    0xa01           8
uscom           DMM1    0xa02           8
usep0           DMM1    0xa04           16
usep1           DMM1    0xa06           16
usep2           DMM1    0xa08           16
usep3           DMM1    0xa0a           16
usber           DMM1    0xa10           16
usbmr           DMM1    0xa14           16
usbs            DMM1    0xa17           8
;
;       SCC2
gsmr_l2         DMM1    0xa20           32
gsmr_h2         DMM1    0xa24           32
psmr2           DMM1    0xa28           16
todr2           DMM1    0xa2c           16
dsr2            DMM1    0xa2e           16
scce2           DMM1    0xa30           16
sccm2           DMM1    0xa34           16
sccs2           DMM1    0xa37           8
irmode          DMM1    0xa38           16
irsip           DMM1    0xa3a           16
;
;       SCC3 (Where applicable)
gsmr_l3         DMM1    0xa40           32
gsmr_h3         DMM1    0xa44           32
psmr3           DMM1    0xa48           16
todr3           DMM1    0xa4c           16
dsr3            DMM1    0xa4e           16
scce3           DMM1    0xa50           16
sccm3           DMM1    0xa54           16
sccs3           DMM1    0xa57           8
;
;       SMC1
smcmr1          DMM1    0xa82           16
smce1           DMM1    0xa86           8
smcm1           DMM1    0xa8a           8
;
;       SMC2
smcmr2          DMM1    0xa92           16
smce2           DMM1    0xa96           8
smcm2           DMM1    0xa9a           8
;
;       SPI
spmode          DMM1    0xaa0           16
spie            DMM1    0xaa6           8
spim            DMM1    0xaaa           8
spcom           DMM1    0xaad           8
;
;       Port B
pbdir		DMM1	0xab8		32
pbpar		DMM1	0xabc		32
pbodr		DMM1	0xac0		32
pbdat		DMM1	0xac4		32
;
;       SI
simode          DMM1    0xae0           32
sigmr           DMM1    0xae4           8
sistr           DMM1    0xae6           8
sicmr           DMM1    0xae7           8
sicr            DMM1    0xaec           32
sirp            DMM1    0xaf0           32
;

