;Register definition for MPC8641 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IMMx indirect memory mapped register ; x = 1..4 ; the addr and data address is defined in the configuration file ; e.g. IMM1 0xFEC00000 0xFEE00000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; xer SPR 1 vscr SPR 2 lr SPR 8 ctr SPR 9 dsisr SPR 18 dar SPR 19 dec SPR 22 sdr1 SPR 25 srr0 SPR 26 srr1 SPR 27 vrsave SPR 256 tbl SPR 268 tbu SPR 269 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 sprg4 SPR 276 sprg5 SPR 277 sprg6 SPR 278 sprg7 SPR 279 ear SPR 282 pvr SPR 287 ; ibat0u SPR 528 ibat0l SPR 529 ibat1u SPR 530 ibat1l SPR 531 ibat2u SPR 532 ibat2l SPR 533 ibat3u SPR 534 ibat3l SPR 535 ; dbat0u SPR 536 dbat0l SPR 537 dbat1u SPR 538 dbat1l SPR 539 dbat2u SPR 540 dbat2l SPR 541 dbat3u SPR 542 dbat3l SPR 543 ; ibat4u SPR 560 ibat4l SPR 561 ibat5u SPR 562 ibat5l SPR 563 ibat6u SPR 564 ibat6l SPR 565 ibat7u SPR 566 ibat7l SPR 567 ; dbat4u SPR 568 dbat4l SPR 569 dbat5u SPR 570 dbat5l SPR 571 dbat6u SPR 572 dbat6l SPR 573 dbat7u SPR 574 dbat7l SPR 575 ; mmcr2 SPR 944 pmc5 SPR 945 pmc6 SPR 946 bamr SPR 951 mmcr0 SPR 952 pmc1 SPR 953 pmc2 SPR 954 siar SPR 955 mmcr1 SPR 956 pmc3 SPR 957 pmc4 SPR 958 ; tlbmiss SPR 980 ptehi SPR 981 ptelo SPR 982 ; hid0 SPR 1008 hid1 SPR 1009 iabr SPR 1010 ictrl SPR 1011 dabr SPR 1013 msscr0 SPR 1014 msssr0 SPR 1015 ldstcr SPR 1016 l2cr SPR 1017 ictc SPR 1019 pir SPR 1023 ; ; ; Local Access Register ccsrbar CCSR 0x00000 altcbar CCSR 0x00008 altcsr CCSR 0x00010 bptr CCSR 0x00020 lawbar0 CCSR 0x00C08 lawar0 CCSR 0x00C10 lawbar1 CCSR 0x00C28 lawar1 CCSR 0x00C30 lawbar2 CCSR 0x00C48 lawar2 CCSR 0x00C50 lawbar3 CCSR 0x00C68 lawar3 CCSR 0x00C70 lawbar4 CCSR 0x00C88 lawar4 CCSR 0x00C90 lawbar5 CCSR 0x00CA8 lawar5 CCSR 0x00CB0 lawbar6 CCSR 0x00CC8 lawsa6 CCSR 0x00CD0 lawbar7 CCSR 0x00CE8 lawsa7 CCSR 0x00CF0 lawbar8 CCSR 0x00D08 lawar8 CCSR 0x00D10 lawbar9 CCSR 0x00D28 lawar9 CCSR 0x00D30 ; ; MPX Coherency Module abcr CCSR 0x01000 dbcr CCSR 0x01008 mcmpcr CCSR 0x01010 edr CCSR 0x01E00 eer CCSR 0x01E08 eatr CCSR 0x01E0C eladr CCSR 0x01E10 ehadr CCSR 0x01E14 ; ; DDR Memory Controller #1 c1_cs0_bnds CCSR 0x02000 c1_cs1_bnds CCSR 0x02008 c1_cs2_bnds CCSR 0x02010 c1_cs3_bnds CCSR 0x02018 c1_cs0_config CCSR 0x02080 c1_cs1_config CCSR 0x02084 c1_cs2_config CCSR 0x02088 c1_cs3_config CCSR 0x0208C c1_timing_cfg_3 CCSR 0x02100 c1_timing_cfg_0 CCSR 0x02104 c1_timing_cfg_1 CCSR 0x02108 c1_timing_cfg_2 CCSR 0x0210C c1_ddr_sdram_cfg CCSR 0x02110 c1_ddr_sdram_cfg_2 CCSR 0x02114 c1_ddr_sdram_mode CCSR 0x02118 c1_ddr_sdram_mode_2 CCSR 0x0211C c1_ddr_sdram_md_cntl CCSR 0x02120 c1_ddr_sdram_interval CCSR 0x02124 c1_ddr_data_init CCSR 0x02128 c1_ddr_sdram_clk_cntl CCSR 0x02130 c1_ddr_init_addr CCSR 0x02148 c1_ddr_init_ext_addr CCSR 0x0214C c1_ddrdsr_1 CCSR 0x02B20 c1_ddrdsr_2 CCSR 0x02B24 c1_ddrcdr_1 CCSR 0x02B28 c1_ddrcdr_2 CCSR 0x02B2C c1_ddr_ip_rev1 CCSR 0x02BF8 c1_ddr_ip_rev2 CCSR 0x02BFC c1_data_err_inject_hi CCSR 0x02E00 c1_data_err_inject_lo CCSR 0x02E04 c1_ecc_err_inject CCSR 0x02E08 c1_capture_data_hi CCSR 0x02E20 c1_capture_data_lo CCSR 0x02E24 c1_capture_ecc CCSR 0x02E28 c1_err_detect CCSR 0x02E40 c1_err_disable CCSR 0x02E44 c1_err_int_en CCSR 0x02E48 c1_capture_attributes CCSR 0x02E4C c1_capture_addr CCSR 0x02E50 c1_capture_ext_addr CCSR 0x02E54 c1_err_sbe CCSR 0x02E58 ; ; DDR Memory Controller #2 c2_cs0_bnds CCSR 0x06000 c2_cs1_bnds CCSR 0x06008 c2_cs2_bnds CCSR 0x06010 c2_cs3_bnds CCSR 0x06018 c2_cs0_config CCSR 0x06080 c2_cs1_config CCSR 0x06084 c2_cs2_config CCSR 0x06088 c2_cs3_config CCSR 0x0608C c2_timing_cfg_3 CCSR 0x06100 c2_timing_cfg_0 CCSR 0x06104 c2_timing_cfg_1 CCSR 0x06108 c2_timing_cfg_2 CCSR 0x0610C c2_ddr_sdram_cfg CCSR 0x06110 c2_ddr_sdram_cfg_2 CCSR 0x06114 c2_ddr_sdram_mode CCSR 0x06118 c2_ddr_sdram_mode_2 CCSR 0x0611C c2_ddr_sdram_md_cntl CCSR 0x06120 c2_ddr_sdram_interval CCSR 0x06124 c2_ddr_data_init CCSR 0x06128 c2_ddr_sdram_clk_cntl CCSR 0x06130 c2_ddr_init_addr CCSR 0x06148 c2_ddr_init_ext_addr CCSR 0x0614C c2_ddrdsr_1 CCSR 0x06B20 c2_ddrdsr_2 CCSR 0x06B24 c2_ddrcdr_1 CCSR 0x06B28 c2_ddrcdr_2 CCSR 0x06B2C c2_ddr_ip_rev1 CCSR 0x06BF8 c2_ddr_ip_rev2 CCSR 0x06BFC c2_data_err_inject_hi CCSR 0x06E00 c2_data_err_inject_lo CCSR 0x06E04 c2_ecc_err_inject CCSR 0x06E08 c2_capture_data_hi CCSR 0x06E20 c2_capture_data_lo CCSR 0x06E24 c2_capture_ecc CCSR 0x06E28 c2_err_detect CCSR 0x06E40 c2_err_disable CCSR 0x06E44 c2_err_int_en CCSR 0x06E48 c2_capture_attributes CCSR 0x06E4C c2_capture_addr CCSR 0x06E50 c2_capture_ext_addr CCSR 0x06E54 c2_err_sbe CCSR 0x06E58 ; ; Local Bus Controller br0 CCSR 0x05000 br1 CCSR 0x05008 br2 CCSR 0x05010 br3 CCSR 0x05018 br4 CCSR 0x05020 br5 CCSR 0x05028 br6 CCSR 0x05030 br7 CCSR 0x05038 or0 CCSR 0x05004 or1 CCSR 0x0500C or2 CCSR 0x05014 or3 CCSR 0x0501C or4 CCSR 0x05024 or5 CCSR 0x0502C or6 CCSR 0x05034 or7 CCSR 0x0503C mar CCSR 0x05068 mamr CCSR 0x05070 mbmr CCSR 0x05074 mcmr CCSR 0x05078 mrtpr CCSR 0x05084 mdr CCSR 0x05088 lsdmr CCSR 0x05094 lurt CCSR 0x050A0 lsrt CCSR 0x050A4 ltesr CCSR 0x050B0 ltedr CCSR 0x050B4 lteir CCSR 0x050B8 lteatr CCSR 0x050BC ltear CCSR 0x050C0 lbcr CCSR 0x050D0 lcrr CCSR 0x050D4 ; ; Power-On Reset Configuration porpllsr CCSR 0xE0000 porbmsr CCSR 0xE0004 porimpcr CCSR 0xE0008 pordevsr CCSR 0xE000C pordbgmsr CCSR 0xE0010 gpporcr CCSR 0xE0020 ; ; Signal Multiplexing and GPIO Controls gpiocr CCSR 0xE0030 gpoutdr CCSR 0xE0040 gpindr CCSR 0xE0050 pmuxcr CCSR 0xE0060 ; ; Device Disables devdisr CCSR 0xE0070 ; ; Power Management powmgtcsr CCSR 0xE0080 ; ; Interrupt and Reset Status and Control mcpsumr CCSR 0xE0090 rstrscr CCSR 0xE0094 mmpvr CCSR 0xE00A0 mmsvr CCSR 0xE00A4 rstcr CCSR 0xE00B0 clkocr CCSR 0xE0E00 ; ; Watchpoint Monitor wmcr0 CCSR 0xE2000 wmcr1 CCSR 0xE2004 wmar CCSR 0xE200C wmamr CCSR 0xE2014 wmtmr CCSR 0xE2018 wmsr CCSR 0xE201C ; ; Trace Buffer tbcr0 CCSR 0xE2040 tbcr1 CCSR 0xE2044 tbar CCSR 0xE204C tbamr CCSR 0xE2054 tbtmr CCSR 0xE2058 tbsr CCSR 0xE205C tbacr CCSR 0xE2060 tbadhr CCSR 0xE2064 tbadr CCSR 0xE2068 tosr CCSR 0xE20B0 ; ; Context ID pcidr CCSR 0xE20A0 ccidr CCSR 0xE20A4